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@ARTICLE{Shamookh:1043081,
      author       = {Shamookh, Muhammad and Ashok, Arun and Zambanini, Andre and
                      Geläschus, Anton and Grewing, Christian and Bahr, Andreas
                      and van Waasen, Stefan},
      title        = {3.35{V} {H}igh {V}oltage {E}lectroforming {S}ystem in 28nm
                      with 5.3m{V} ripple and 46 $\%$ efficiency for {H}2{O}-based
                      {M}emristors},
      journal      = {International journal of electronics and communications},
      volume       = {200},
      issn         = {1434-8411},
      publisher    = {Elsevier},
      reportid     = {FZJ-2025-02767},
      pages        = {155863},
      year         = {2025},
      abstract     = {This work demonstrates an on-chip high voltage (HV)
                      generation, which is a critical requirement for memristor
                      electroforming (EF) but is typically absent in smaller
                      technology nodes. Key achievements of this study includes:
                      1) the development of a three-stage charge pump (CP) with an
                      efficiency of $46.5\%,$ delivering an EF voltage VEF of 3.35
                      V with a compliance current Icc of 184.9 μA from a 1.8 V
                      supply voltage Vdd, without the need for HV-transistors in
                      28 nm CMOS process, and is based on preliminary work
                      presented at the 20th International Conference on Synthesis,
                      Modeling, Analysis and Simulation Methods and Applications
                      to Circuit Design (SMACD) in Volos, Greece [1]; 2) the
                      electrostatic discharge (ESD) protection, meeting the
                      requirements of Class C3 CDM (±300 V) and Class 1C HBM
                      (±1.5 kV) as per JEDEC standards [2], employing three ESD
                      diodes to handle positive (> 3.3 V) triggering ESD events
                      and a single ESD diode for negative triggering ESD events
                      above −1.87 V; and 3) the on-chip EF architecture for a 64
                      × 64 memristor crossbar array, as an active matrix (AM),
                      through source and gate control of the compliance
                      transistor. A ripple detection stage monitors voltage ripple
                      at the three-stage CP bit-line (BL), halting gate pulses to
                      the active compliance transistor and triggering EF for the
                      next memristor in the left-to-right sequence. The proposed
                      design is scalable to any m × n array and adaptable to
                      various memristor applications, paving the way for fully
                      integrated EF solutions in advanced technology nodes.},
      cin          = {PGI-4},
      ddc          = {620},
      cid          = {I:(DE-Juel1)PGI-4-20110106},
      pnm          = {5234 - Emerging NC Architectures (POF4-523) / BMBF
                      16ME0398K - Verbundprojekt: Neuro-inspirierte Technologien
                      der künstlichen Intelligenz für die Elektronik der Zukunft
                      - NEUROTEC II - (BMBF-16ME0398K)},
      pid          = {G:(DE-HGF)POF4-5234 / G:(DE-82)BMBF-16ME0398K},
      typ          = {PUB:(DE-HGF)16},
      UT           = {WOS:001510502500002},
      doi          = {10.1016/j.aeue.2025.155863},
      url          = {https://juser.fz-juelich.de/record/1043081},
}