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@ARTICLE{Gebrewold:1044645,
      author       = {Gebrewold, Habtamu Tsegaye and Bittkau, Karsten and
                      Lambertz, Andreas and Rau, Uwe and Ding, Kaining},
      title        = {{D}etailed {B}ias‐{D}ependent {F}ree {E}nergy {L}oss
                      {A}nalysis for {P}roposing {D}evice {O}ptimization
                      {S}trategies in {S}ilicon {H}eterojunction {S}olar {C}ell
                      {D}esign},
      journal      = {Solar RRL},
      volume       = {9},
      number       = {15},
      issn         = {2367-198X},
      address      = {Weinheim},
      publisher    = {Wiley-VCH},
      reportid     = {FZJ-2025-03309},
      pages        = {202500311},
      year         = {2025},
      abstract     = {A multiscale electro-optical device model is employed to
                      investigate free energy and other losses in a silicon
                      heterojunction (SHJ) solar cell. A finite element
                      method-based device model is coupled with free energy loss
                      analysis (FELA) to calculate detailed bias voltage-dependent
                      losses in terms of mAcm-2 and mWcm-2. Such an approach
                      provides insight into identifying possible pathways for
                      synergetic optimization and redesigning a solar cell device
                      in both laboratory and mass production settings. The SHJ
                      solar cell investigated in this work demonstrates that the
                      hole-selective contact (HSC) is responsible for a
                      significant portion of the free energy loss. At maximum
                      power point, a power density of ~1.6 mWcm-2 at 1 sun is lost
                      associated with carrier transport in HSC and recombination
                      at both selective contacts. This results in a $1.6\%$
                      absolute loss in power conversion efficiency (PCE). Auger
                      recombination in the wafer limits the open-circuit voltage.
                      The FELA suggests a pathway for synergistic optimization of
                      the device to regain a significant portion of the $~2.6\%$
                      absolute loss in PCE. Simultaneously adjusting the
                      conductivity of a-Si layers in HSC and the concentration of
                      free majority carriers in the wafer can improve the fill
                      factor (FF) to $~87\%$ and PCE close to $26\%.$},
      cin          = {IMD-3},
      ddc          = {600},
      cid          = {I:(DE-Juel1)IMD-3-20101013},
      pnm          = {1215 - Simulations, Theory, Optics, and Analytics (STOA)
                      (POF4-121)},
      pid          = {G:(DE-HGF)POF4-1215},
      typ          = {PUB:(DE-HGF)16},
      doi          = {10.1002/solr.202500311},
      url          = {https://juser.fz-juelich.de/record/1044645},
}