Home > Publications database > Co-Simulation for Automated Optimization of Integrated Cryogenic Qubit Electronics > print |
001 | 1044889 | ||
005 | 20250922202049.0 | ||
020 | _ | _ | |a 979-8-3315-2395-4 |
024 | 7 | _ | |a 10.1109/SMACD65553.2025.11092223 |2 doi |
037 | _ | _ | |a FZJ-2025-03423 |
041 | _ | _ | |a English |
100 | 1 | _ | |a Dietz Romero, Pau |0 P:(DE-Juel1)204256 |b 0 |e Corresponding author |
111 | 2 | _ | |a 2025 21st International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuits Design (SMACD) |g SMACD |c Istanbul |d 2025-07-07 - 2025-07-10 |w Turkiye |
245 | _ | _ | |a Co-Simulation for Automated Optimization of Integrated Cryogenic Qubit Electronics |
260 | _ | _ | |c 2025 |b IEEE |
300 | _ | _ | |a 4 |
336 | 7 | _ | |a CONFERENCE_PAPER |2 ORCID |
336 | 7 | _ | |a Conference Paper |0 33 |2 EndNote |
336 | 7 | _ | |a INPROCEEDINGS |2 BibTeX |
336 | 7 | _ | |a conferenceObject |2 DRIVER |
336 | 7 | _ | |a Output Types/Conference Paper |2 DataCite |
336 | 7 | _ | |a Contribution to a conference proceedings |b contrib |m contrib |0 PUB:(DE-HGF)8 |s 1758524884_18435 |2 PUB:(DE-HGF) |
336 | 7 | _ | |a Contribution to a book |0 PUB:(DE-HGF)7 |2 PUB:(DE-HGF) |m contb |
520 | _ | _ | |a One approach to scaling quantum computers requires large-scale integration of qubit control electronics at cryogenic temperatures close to the qubits to reduce the wiring bottleneck, signal latencies, and improve the modularity of the system. Finding optimized specifications by accurately simulating the qubit-electronics interface allows optimal budgeting of resources (heat dissipation, area) for scalable quantum computers. We propose a systematic and efficient design flow for the optimization of integrated electronic circuits using a co-simulation methodology that covers the entire development process from the concept phase to transistor-level design. As a use case, we choose the shuttling of spin qubits inside quantum dots. The automated workflow optimizes the hardware parameters of the circuit during the design phase of the integrated circuit. Based on the simulated performance of our low-power circuits, we argue that well-designed integrated electronics can replace critically-scaling room-temperature electronics for the given use case. |
536 | _ | _ | |a 5223 - Quantum-Computer Control Systems and Cryoelectronics (POF4-522) |0 G:(DE-HGF)POF4-5223 |c POF4-522 |f POF IV |x 0 |
588 | _ | _ | |a Dataset connected to CrossRef Conference |
700 | 1 | _ | |a Toprak, Caner |0 P:(DE-Juel1)199845 |b 1 |
700 | 1 | _ | |a Duipmans, Lammert |0 P:(DE-Juel1)186966 |b 2 |
700 | 1 | _ | |a van Waasen, Stefan |0 P:(DE-Juel1)142562 |b 3 |
700 | 1 | _ | |a Geck, Lotte |0 P:(DE-Juel1)169123 |b 4 |
773 | _ | _ | |a 10.1109/SMACD65553.2025.11092223 |
856 | 4 | _ | |u https://ieeexplore.ieee.org/abstract/document/11092223 |
909 | C | O | |o oai:juser.fz-juelich.de:1044889 |p VDB |
910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 0 |6 P:(DE-Juel1)204256 |
910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 1 |6 P:(DE-Juel1)199845 |
910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 2 |6 P:(DE-Juel1)186966 |
910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 3 |6 P:(DE-Juel1)142562 |
910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 4 |6 P:(DE-Juel1)169123 |
913 | 1 | _ | |a DE-HGF |b Key Technologies |l Natural, Artificial and Cognitive Information Processing |1 G:(DE-HGF)POF4-520 |0 G:(DE-HGF)POF4-522 |3 G:(DE-HGF)POF4 |2 G:(DE-HGF)POF4-500 |4 G:(DE-HGF)POF |v Quantum Computing |9 G:(DE-HGF)POF4-5223 |x 0 |
914 | 1 | _ | |y 2025 |
920 | _ | _ | |l yes |
920 | 1 | _ | |0 I:(DE-Juel1)PGI-4-20110106 |k PGI-4 |l Integrated Computing Architectures |x 0 |
980 | _ | _ | |a contrib |
980 | _ | _ | |a VDB |
980 | _ | _ | |a contb |
980 | _ | _ | |a I:(DE-Juel1)PGI-4-20110106 |
980 | _ | _ | |a UNRESTRICTED |
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