%0 Conference Paper
%A Chava, Phanish
%A Alius, Heidrun
%A Gneiting, Thomas
%A Heide, Thomas
%A Javorka, Peter
%A Kessler, Matthias
%A Lederer, Maximilian
%A Lehmann, Steffen
%A Simon, Maik
%A Su, Meng
%A Vliex, Patrick
%A van Waasen, Stefan
%A Witt, Christian
%A Zetzsche, Dennis
%T Cryogenic Performance Assessment of FD-SOI Transistors with Counter-Doped Channel
%I IEEE
%M FZJ-2025-04447
%P 261-264
%D 2025
%X We investigate the cryogenic performance of Fully Depleted Silicon-on-Insulator (FD-SOI) transistors, focusing on devices featuring counter-doped channels. We explore counterdoping as a potential strategy to mitigate the increased threshold voltage at cryogenic temperatures, aiming to reduce power consumption. We extract key performance metrics such as threshold voltage, subthreshold swing, and other relevant parameters from cryogenic measurements, and compare them against conventional FD-SOI devices. Our results demonstrate that counter-doping enables effective threshold voltage control without compromising electrical performance, positioning it as a promising solution for ultra-low-power cryogenic CMOS optimization in scalable quantum computing applications.
%B 2025 IEEE European Solid-State Electronics Research Conference (ESSERC)
%C 8 Sep 2025 - 11 Sep 2025, Munich (Germany)
Y2 8 Sep 2025 - 11 Sep 2025
M2 Munich, Germany
%F PUB:(DE-HGF)8
%9 Contribution to a conference proceedings
%R 10.1109/ESSERC66193.2025.11214120
%U https://juser.fz-juelich.de/record/1047672