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001047672 005__ 20251202203135.0
001047672 0247_ $$2doi$$a10.1109/ESSERC66193.2025.11214120
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001047672 1001_ $$0P:(DE-Juel1)196006$$aChava, Phanish$$b0$$ufzj
001047672 1112_ $$a2025 IEEE European Solid-State Electronics Research Conference (ESSERC)$$cMunich$$d2025-09-08 - 2025-09-11$$wGermany
001047672 245__ $$aCryogenic Performance Assessment of FD-SOI Transistors with Counter-Doped Channel
001047672 260__ $$bIEEE$$c2025
001047672 300__ $$a261-264
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001047672 520__ $$aWe investigate the cryogenic performance of Fully Depleted Silicon-on-Insulator (FD-SOI) transistors, focusing on devices featuring counter-doped channels. We explore counterdoping as a potential strategy to mitigate the increased threshold voltage at cryogenic temperatures, aiming to reduce power consumption. We extract key performance metrics such as threshold voltage, subthreshold swing, and other relevant parameters from cryogenic measurements, and compare them against conventional FD-SOI devices. Our results demonstrate that counter-doping enables effective threshold voltage control without compromising electrical performance, positioning it as a promising solution for ultra-low-power cryogenic CMOS optimization in scalable quantum computing applications.
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001047672 7001_ $$0P:(DE-HGF)0$$aAlius, Heidrun$$b1
001047672 7001_ $$0P:(DE-HGF)0$$aGneiting, Thomas$$b2
001047672 7001_ $$0P:(DE-HGF)0$$aHeide, Thomas$$b3
001047672 7001_ $$0P:(DE-HGF)0$$aJavorka, Peter$$b4
001047672 7001_ $$0P:(DE-HGF)0$$aKessler, Matthias$$b5
001047672 7001_ $$0P:(DE-HGF)0$$aLederer, Maximilian$$b6
001047672 7001_ $$0P:(DE-HGF)0$$aLehmann, Steffen$$b7
001047672 7001_ $$0P:(DE-HGF)0$$aSimon, Maik$$b8
001047672 7001_ $$0P:(DE-HGF)0$$aSu, Meng$$b9
001047672 7001_ $$0P:(DE-Juel1)171680$$aVliex, Patrick$$b10$$ufzj
001047672 7001_ $$0P:(DE-Juel1)142562$$avan Waasen, Stefan$$b11$$ufzj
001047672 7001_ $$0P:(DE-HGF)0$$aWitt, Christian$$b12
001047672 7001_ $$0P:(DE-HGF)0$$aZetzsche, Dennis$$b13
001047672 773__ $$a10.1109/ESSERC66193.2025.11214120
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