TY  - CONF
AU  - Chava, Phanish
AU  - Alius, Heidrun
AU  - Gneiting, Thomas
AU  - Heide, Thomas
AU  - Javorka, Peter
AU  - Kessler, Matthias
AU  - Lederer, Maximilian
AU  - Lehmann, Steffen
AU  - Simon, Maik
AU  - Su, Meng
AU  - Vliex, Patrick
AU  - van Waasen, Stefan
AU  - Witt, Christian
AU  - Zetzsche, Dennis
TI  - Cryogenic Performance Assessment of FD-SOI Transistors with Counter-Doped Channel
PB  - IEEE
M1  - FZJ-2025-04447
SP  - 261-264
PY  - 2025
AB  - We investigate the cryogenic performance of Fully Depleted Silicon-on-Insulator (FD-SOI) transistors, focusing on devices featuring counter-doped channels. We explore counterdoping as a potential strategy to mitigate the increased threshold voltage at cryogenic temperatures, aiming to reduce power consumption. We extract key performance metrics such as threshold voltage, subthreshold swing, and other relevant parameters from cryogenic measurements, and compare them against conventional FD-SOI devices. Our results demonstrate that counter-doping enables effective threshold voltage control without compromising electrical performance, positioning it as a promising solution for ultra-low-power cryogenic CMOS optimization in scalable quantum computing applications.
T2  - 2025 IEEE European Solid-State Electronics Research Conference (ESSERC)
CY  - 8 Sep 2025 - 11 Sep 2025, Munich (Germany)
Y2  - 8 Sep 2025 - 11 Sep 2025
M2  - Munich, Germany
LB  - PUB:(DE-HGF)8
DO  - DOI:10.1109/ESSERC66193.2025.11214120
UR  - https://juser.fz-juelich.de/record/1047672
ER  -