001     1047672
005     20251202203135.0
024 7 _ |a 10.1109/ESSERC66193.2025.11214120
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037 _ _ |a FZJ-2025-04447
100 1 _ |a Chava, Phanish
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111 2 _ |a 2025 IEEE European Solid-State Electronics Research Conference (ESSERC)
|c Munich
|d 2025-09-08 - 2025-09-11
|w Germany
245 _ _ |a Cryogenic Performance Assessment of FD-SOI Transistors with Counter-Doped Channel
260 _ _ |c 2025
|b IEEE
300 _ _ |a 261-264
336 7 _ |a CONFERENCE_PAPER
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520 _ _ |a We investigate the cryogenic performance of Fully Depleted Silicon-on-Insulator (FD-SOI) transistors, focusing on devices featuring counter-doped channels. We explore counterdoping as a potential strategy to mitigate the increased threshold voltage at cryogenic temperatures, aiming to reduce power consumption. We extract key performance metrics such as threshold voltage, subthreshold swing, and other relevant parameters from cryogenic measurements, and compare them against conventional FD-SOI devices. Our results demonstrate that counter-doping enables effective threshold voltage control without compromising electrical performance, positioning it as a promising solution for ultra-low-power cryogenic CMOS optimization in scalable quantum computing applications.
536 _ _ |a 5223 - Quantum-Computer Control Systems and Cryoelectronics (POF4-522)
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588 _ _ |a Dataset connected to CrossRef Conference
700 1 _ |a Alius, Heidrun
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700 1 _ |a Gneiting, Thomas
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700 1 _ |a Heide, Thomas
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700 1 _ |a Javorka, Peter
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700 1 _ |a Kessler, Matthias
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700 1 _ |a Lederer, Maximilian
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700 1 _ |a Lehmann, Steffen
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700 1 _ |a Simon, Maik
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700 1 _ |a Su, Meng
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700 1 _ |a Vliex, Patrick
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700 1 _ |a van Waasen, Stefan
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700 1 _ |a Witt, Christian
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700 1 _ |a Zetzsche, Dennis
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773 _ _ |a 10.1109/ESSERC66193.2025.11214120
856 4 _ |u https://juser.fz-juelich.de/record/1047672/files/Paper.pdf
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913 1 _ |a DE-HGF
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914 1 _ |y 2025
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