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001048886 005__ 20251204202147.0
001048886 0247_ $$2doi$$a10.1109/QCE65121.2025.00121
001048886 037__ $$aFZJ-2025-04991
001048886 1001_ $$0P:(DE-Juel1)169123$$aGeck, Lotte$$b0$$eCorresponding author
001048886 1112_ $$a2025 IEEE International Conference on Quantum Computing and Engineering (QCE)$$cAlbuquerque, NM$$d2025-08-30 - 2025-09-05$$wUSA
001048886 245__ $$aPartitioning Cryogenic Integrated Electronics for Scalable Spin Qubit Operation
001048886 260__ $$bIEEE$$c2025
001048886 300__ $$a1083-1088
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001048886 520__ $$aA systematic investigation of currently implemented cryogenic electronics for controlling and reading out spin qubits using complementary metal-oxide semiconductor (CMOS) technology is done. Scalability is the primary focus in developing these circuits, as enabling universal quantum computing requires increasing the number of qubits by several orders of magnitude. Low power dissipation is a main quality benchmark for cryogenic circuits that is being optimized. Next to that, the possibility of connecting multiple control signals to each qubit is a challenge for large qubit numbers. Depending on the placement of the electronics, different power budgets and connectivity options are available. These characteristics are used to discuss medium and long-term use-cases for existing designs and what future concepts and developments might be possible or necessary for full scalability on the example of spin qubit operation electronics.
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001048886 7001_ $$0P:(DE-Juel1)204256$$aDietz Romero, Pau$$b1
001048886 7001_ $$0P:(DE-Juel1)186966$$aDuipmans, Lammert$$b2$$ufzj
001048886 7001_ $$0P:(DE-Juel1)142562$$avan Waasen, Stefan$$b3$$ufzj
001048886 773__ $$a10.1109/QCE65121.2025.00121
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001048886 9141_ $$y2025
001048886 9201_ $$0I:(DE-Juel1)PGI-4-20110106$$kPGI-4$$lIntegrated Computing Architectures$$x0
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