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| Hauptseite > Publikationsdatenbank > Optimizing Edge AI Models on HPC Systems with the Edge in the Loop > print |
| Hauptseite > Publikationsdatenbank > Optimizing Edge AI Models on HPC Systems with the Edge in the Loop > print |
| 001 | 1048916 | ||
| 005 | 20251219202230.0 | ||
| 020 | _ | _ | |a 978-3-032-07611-3 (print) |
| 020 | _ | _ | |a 978-3-032-07612-0 (electronic) |
| 024 | 7 | _ | |a 10.1007/978-3-032-07612-0_12 |2 doi |
| 024 | 7 | _ | |a 0302-9743 |2 ISSN |
| 024 | 7 | _ | |a 1611-3349 |2 ISSN |
| 024 | 7 | _ | |a 10.34734/FZJ-2025-05015 |2 datacite_doi |
| 037 | _ | _ | |a FZJ-2025-05015 |
| 041 | _ | _ | |a English |
| 100 | 1 | _ | |a Aach, Marcel |0 P:(DE-Juel1)180916 |b 0 |e Corresponding author |u fzj |
| 111 | 2 | _ | |a ISC High Performance 2025 |g ISC 2025 |c Hamburg |d 2025-06-10 - 2025-06-13 |w Germany |
| 245 | _ | _ | |a Optimizing Edge AI Models on HPC Systems with the Edge in the Loop |
| 260 | _ | _ | |a Cham |c 2026 |b Springer Nature Switzerland |
| 295 | 1 | 0 | |a High Performance Computing |
| 300 | _ | _ | |a 148 - 161 |
| 336 | 7 | _ | |a CONFERENCE_PAPER |2 ORCID |
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| 490 | 0 | _ | |a Lecture Notes in Computer Science |v 16091 |
| 520 | _ | _ | |a Artificial Intelligence (AI) and Machine Learning (ML) models deployed on edge devices, e.g., for quality control in Additive Manufacturing (AM), are frequently small in size. Such models usually have to deliver highly accurate results within a short time frame. Methodsthat are commonly employed in literature start out with larger trained models and try to reduce their memory and latency footprint by structural pruning, knowledge distillation, or quantization. It is, however, also possible to leverage hardware-aware Neural Architecture Search (NAS), an approach that seeks to systematically explore the architecture space to find optimized configurations. In this study, a hardware-aware NAS workflow is introduced that couples an edge device located in Belgium with a powerful High-Performance Computing (HPC) system in Germany, to train possible architecture candidates as fast as possible while performing real-time latency measurements on the target hardware. The approach is verified on a use case in the AM domain, based on the open RAISE-LPBF dataset, achieving ≈ 8.8 times faster inference speed while simultaneously enhancing model quality by a factor of ≈ 1.35, compared to a human-designed baseline. |
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| 536 | _ | _ | |a RAISE - Research on AI- and Simulation-Based Engineering at Exascale (951733) |0 G:(EU-Grant)951733 |c 951733 |f H2020-INFRAEDI-2019-1 |x 1 |
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| 700 | 1 | _ | |a Blanc, Cyril |0 0000-0003-3271-2398 |b 1 |
| 700 | 1 | _ | |a Lintermann, Andreas |0 P:(DE-Juel1)165948 |b 2 |
| 700 | 1 | _ | |a De Grave, Kurt |0 0000-0001-9116-6986 |b 3 |
| 770 | _ | _ | |z 978-3-032-07611-3 |
| 773 | _ | _ | |a 10.1007/978-3-032-07612-0_12 |
| 856 | 4 | _ | |u https://juser.fz-juelich.de/record/1048916/files/2505.19995v1.pdf |y OpenAccess |
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