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@INPROCEEDINGS{Schlepphorst:1049771,
      author       = {Schlepphorst, Simon and Krieg, Stefan},
      title        = {{P}orting {L}attice {QCD} benchmark to upcoming {STX}
                      stencil/tensor accelerator},
      address      = {Trieste, Italy},
      publisher    = {Sissa Medialab Trieste, Italy},
      reportid     = {FZJ-2025-05555},
      pages        = {451 pp.},
      year         = {2025},
      comment      = {Proceedings of The 41st International Symposium on Lattice
                      Field Theory — PoS(LATTICE2024)},
      booktitle     = {Proceedings of The 41st International
                       Symposium on Lattice Field Theory —
                       PoS(LATTICE2024)},
      abstract     = {Developed under the European Processor Initiative (EPI),
                      the STX stencil/tensor accelerator aims to achieve a 5-10x
                      higher energy efficiency over general purpose compute units.
                      The architecture consists of specialized MIMD compute units
                      which are supported and controlled by RISC-V cores. We
                      describe a co-design effort between hardware, software, and
                      application development focused around porting a LQCD
                      benchmark to this new architecture.},
      month         = {Jul},
      date          = {2024-07-28},
      organization  = {The 41st International Symposium on
                       Lattice Field Theory, Liverpool (UK),
                       28 Jul 2024 - 3 Aug 2024},
      cin          = {JSC},
      cid          = {I:(DE-Juel1)JSC-20090406},
      pnm          = {5111 - Domain-Specific Simulation $\&$ Data Life Cycle Labs
                      (SDLs) and Research Groups (POF4-511) / DFG project
                      G:(GEPRIS)460248186 - PUNCH4NFDI - Teilchen, Universum,
                      Kerne und Hadronen für die NFDI (460248186) / EPI SGA2
                      (16ME0507K) / STXDemo - Energieoptimierte
                      Supercomputer-Hardware durch Stencil- und
                      Tensor-Beschleuniger (BMFTR-16ME0605)},
      pid          = {G:(DE-HGF)POF4-5111 / G:(GEPRIS)460248186 /
                      G:(BMBF)16ME0507K / G:(DE-Juel1)BMFTR-16ME0605},
      typ          = {PUB:(DE-HGF)8 / PUB:(DE-HGF)7},
      doi          = {10.22323/1.466.0451},
      url          = {https://juser.fz-juelich.de/record/1049771},
}