001050049 001__ 1050049
001050049 005__ 20251219155726.0
001050049 0247_ $$2doi$$a10.23919/ISC.2025.11018303
001050049 037__ $$aFZJ-2025-05763
001050049 1001_ $$0P:(DE-Juel1)184395$$aSchätzle, Fabian$$b0$$eCorresponding author
001050049 1112_ $$aISC High Performance 2025 Research Paper Proceedings (40th International Conference)$$cHamburg$$d2025-06-10 - 2025-06-13$$wGermany
001050049 245__ $$aModeling Chiplet-to-Chiplet (C2C) Communication for Chiplet-based Co-Design
001050049 260__ $$bIEEE$$c2025
001050049 29510 $$aISC High Performance 2025 Research Paper Proceedings (40th International Conference) - IEEE, 2025. - ISBN 978-3-9826336-1-9 - doi:10.23919/ISC.2025.11018303
001050049 300__ $$a11
001050049 3367_ $$2ORCID$$aCONFERENCE_PAPER
001050049 3367_ $$033$$2EndNote$$aConference Paper
001050049 3367_ $$2BibTeX$$aINPROCEEDINGS
001050049 3367_ $$2DRIVER$$aconferenceObject
001050049 3367_ $$2DataCite$$aOutput Types/Conference Paper
001050049 3367_ $$0PUB:(DE-HGF)8$$2PUB:(DE-HGF)$$aContribution to a conference proceedings$$bcontrib$$mcontrib$$s1766155978_15646
001050049 3367_ $$0PUB:(DE-HGF)7$$2PUB:(DE-HGF)$$aContribution to a book$$mcontb
001050049 520__ $$aChiplet-based processor design, which combines small dies called chiplets to form a larger chip, enables scalable designs at economical costs. This trend has received high attention such that standards for chiplet design have rapidly established, including packaging, protocols, and Chiplet-to-Chiplet (C2C) interfaces. With numerous well-defined chiplet options available, hardware architects would leverage on the co-design process to make optimal decisions on design parameters. An important performance limitation in multi-chiplet designs come from the protocol translation in the C2C communication, needed to maintain cache coherency and avoid risk of deadlocks. When integrating multiple chiplets, deadlocks can happen from both protocol and routing, making deadlock-free designs important. This paper tackles these challenges by introducing a Chiplet-to-Chiplet Gateway (C2CG) architecture, a C2C interface that bridges two chiplet protocols and ensures deadlock-free C2C communication. We also extend the Coherent Hub Interface (CHI) protocol to support cache coherent data sharing among cores across chiplets. The complete design is implemented in the gem5 simulator, constructing a modeling tool for chiplet-based co-design targeting next-generation High-performance Computing (HPC) processors. We demonstrate the benefit of the model through a design space exploration of three 64-core Armv8 HPC processor configurations: monolithic, two- and four-chiplet. The exploration, using representative HPC benchmarks, provides insights into C2C parameters and studies the impact of Non-Uniform Memory Access (NUMA) configuration, giving valuable co-design feedback for hardware architects.
001050049 536__ $$0G:(DE-HGF)POF4-5234$$a5234 - Emerging NC Architectures (POF4-523)$$cPOF4-523$$fPOF IV$$x0
001050049 536__ $$0G:(DE-HGF)POF4-5122$$a5122 - Future Computing & Big Data Systems (POF4-512)$$cPOF4-512$$fPOF IV$$x1
001050049 588__ $$aDataset connected to CrossRef Conference
001050049 7001_ $$0P:(DE-Juel1)179531$$aFalquez, Carlos$$b1
001050049 7001_ $$0P:(DE-Juel1)176469$$aHo, Nam$$b2$$ufzj
001050049 7001_ $$0P:(DE-Juel1)145837$$aZambanini, André$$b3
001050049 7001_ $$0P:(DE-Juel1)162349$$avan den Boom, Johannes$$b4
001050049 7001_ $$0P:(DE-Juel1)142361$$aSuarez, Estela$$b5
001050049 773__ $$a10.23919/ISC.2025.11018303
001050049 8564_ $$uhttps://ieeexplore.ieee.org/abstract/document/11018303
001050049 8564_ $$uhttps://juser.fz-juelich.de/record/1050049/files/Post-Print.pdf$$yRestricted
001050049 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)184395$$aForschungszentrum Jülich$$b0$$kFZJ
001050049 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)179531$$aForschungszentrum Jülich$$b1$$kFZJ
001050049 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)176469$$aForschungszentrum Jülich$$b2$$kFZJ
001050049 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)145837$$aForschungszentrum Jülich$$b3$$kFZJ
001050049 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)162349$$aForschungszentrum Jülich$$b4$$kFZJ
001050049 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)142361$$aForschungszentrum Jülich$$b5$$kFZJ
001050049 9131_ $$0G:(DE-HGF)POF4-523$$1G:(DE-HGF)POF4-520$$2G:(DE-HGF)POF4-500$$3G:(DE-HGF)POF4$$4G:(DE-HGF)POF$$9G:(DE-HGF)POF4-5234$$aDE-HGF$$bKey Technologies$$lNatural, Artificial and Cognitive Information Processing$$vNeuromorphic Computing and Network Dynamics$$x0
001050049 9131_ $$0G:(DE-HGF)POF4-512$$1G:(DE-HGF)POF4-510$$2G:(DE-HGF)POF4-500$$3G:(DE-HGF)POF4$$4G:(DE-HGF)POF$$9G:(DE-HGF)POF4-5122$$aDE-HGF$$bKey Technologies$$lEngineering Digital Futures – Supercomputing, Data Management and Information Security for Knowledge and Action$$vSupercomputing & Big Data Infrastructures$$x1
001050049 920__ $$lyes
001050049 9201_ $$0I:(DE-Juel1)PGI-4-20110106$$kPGI-4$$lIntegrated Computing Architectures$$x0
001050049 9201_ $$0I:(DE-Juel1)JSC-20090406$$kJSC$$lJülich Supercomputing Center$$x1
001050049 980__ $$acontrib
001050049 980__ $$aEDITORS
001050049 980__ $$aVDBINPRINT
001050049 980__ $$acontb
001050049 980__ $$aI:(DE-Juel1)PGI-4-20110106
001050049 980__ $$aI:(DE-Juel1)JSC-20090406
001050049 980__ $$aUNRESTRICTED