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| 001 | 1050049 | ||
| 005 | 20251219155726.0 | ||
| 024 | 7 | _ | |a 10.23919/ISC.2025.11018303 |2 doi |
| 037 | _ | _ | |a FZJ-2025-05763 |
| 100 | 1 | _ | |a Schätzle, Fabian |0 P:(DE-Juel1)184395 |b 0 |e Corresponding author |
| 111 | 2 | _ | |a ISC High Performance 2025 Research Paper Proceedings (40th International Conference) |c Hamburg |d 2025-06-10 - 2025-06-13 |w Germany |
| 245 | _ | _ | |a Modeling Chiplet-to-Chiplet (C2C) Communication for Chiplet-based Co-Design |
| 260 | _ | _ | |c 2025 |b IEEE |
| 295 | 1 | 0 | |a ISC High Performance 2025 Research Paper Proceedings (40th International Conference) - IEEE, 2025. - ISBN 978-3-9826336-1-9 - doi:10.23919/ISC.2025.11018303 |
| 300 | _ | _ | |a 11 |
| 336 | 7 | _ | |a CONFERENCE_PAPER |2 ORCID |
| 336 | 7 | _ | |a Conference Paper |0 33 |2 EndNote |
| 336 | 7 | _ | |a INPROCEEDINGS |2 BibTeX |
| 336 | 7 | _ | |a conferenceObject |2 DRIVER |
| 336 | 7 | _ | |a Output Types/Conference Paper |2 DataCite |
| 336 | 7 | _ | |a Contribution to a conference proceedings |b contrib |m contrib |0 PUB:(DE-HGF)8 |s 1766155978_15646 |2 PUB:(DE-HGF) |
| 336 | 7 | _ | |a Contribution to a book |0 PUB:(DE-HGF)7 |2 PUB:(DE-HGF) |m contb |
| 520 | _ | _ | |a Chiplet-based processor design, which combines small dies called chiplets to form a larger chip, enables scalable designs at economical costs. This trend has received high attention such that standards for chiplet design have rapidly established, including packaging, protocols, and Chiplet-to-Chiplet (C2C) interfaces. With numerous well-defined chiplet options available, hardware architects would leverage on the co-design process to make optimal decisions on design parameters. An important performance limitation in multi-chiplet designs come from the protocol translation in the C2C communication, needed to maintain cache coherency and avoid risk of deadlocks. When integrating multiple chiplets, deadlocks can happen from both protocol and routing, making deadlock-free designs important. This paper tackles these challenges by introducing a Chiplet-to-Chiplet Gateway (C2CG) architecture, a C2C interface that bridges two chiplet protocols and ensures deadlock-free C2C communication. We also extend the Coherent Hub Interface (CHI) protocol to support cache coherent data sharing among cores across chiplets. The complete design is implemented in the gem5 simulator, constructing a modeling tool for chiplet-based co-design targeting next-generation High-performance Computing (HPC) processors. We demonstrate the benefit of the model through a design space exploration of three 64-core Armv8 HPC processor configurations: monolithic, two- and four-chiplet. The exploration, using representative HPC benchmarks, provides insights into C2C parameters and studies the impact of Non-Uniform Memory Access (NUMA) configuration, giving valuable co-design feedback for hardware architects. |
| 536 | _ | _ | |a 5234 - Emerging NC Architectures (POF4-523) |0 G:(DE-HGF)POF4-5234 |c POF4-523 |f POF IV |x 0 |
| 536 | _ | _ | |a 5122 - Future Computing & Big Data Systems (POF4-512) |0 G:(DE-HGF)POF4-5122 |c POF4-512 |f POF IV |x 1 |
| 588 | _ | _ | |a Dataset connected to CrossRef Conference |
| 700 | 1 | _ | |a Falquez, Carlos |0 P:(DE-Juel1)179531 |b 1 |
| 700 | 1 | _ | |a Ho, Nam |0 P:(DE-Juel1)176469 |b 2 |u fzj |
| 700 | 1 | _ | |a Zambanini, André |0 P:(DE-Juel1)145837 |b 3 |
| 700 | 1 | _ | |a van den Boom, Johannes |0 P:(DE-Juel1)162349 |b 4 |
| 700 | 1 | _ | |a Suarez, Estela |0 P:(DE-Juel1)142361 |b 5 |
| 773 | _ | _ | |a 10.23919/ISC.2025.11018303 |
| 856 | 4 | _ | |u https://ieeexplore.ieee.org/abstract/document/11018303 |
| 856 | 4 | _ | |u https://juser.fz-juelich.de/record/1050049/files/Post-Print.pdf |y Restricted |
| 910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 0 |6 P:(DE-Juel1)184395 |
| 910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 1 |6 P:(DE-Juel1)179531 |
| 910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 2 |6 P:(DE-Juel1)176469 |
| 910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 3 |6 P:(DE-Juel1)145837 |
| 910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 4 |6 P:(DE-Juel1)162349 |
| 910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 5 |6 P:(DE-Juel1)142361 |
| 913 | 1 | _ | |a DE-HGF |b Key Technologies |l Natural, Artificial and Cognitive Information Processing |1 G:(DE-HGF)POF4-520 |0 G:(DE-HGF)POF4-523 |3 G:(DE-HGF)POF4 |2 G:(DE-HGF)POF4-500 |4 G:(DE-HGF)POF |v Neuromorphic Computing and Network Dynamics |9 G:(DE-HGF)POF4-5234 |x 0 |
| 913 | 1 | _ | |a DE-HGF |b Key Technologies |l Engineering Digital Futures – Supercomputing, Data Management and Information Security for Knowledge and Action |1 G:(DE-HGF)POF4-510 |0 G:(DE-HGF)POF4-512 |3 G:(DE-HGF)POF4 |2 G:(DE-HGF)POF4-500 |4 G:(DE-HGF)POF |v Supercomputing & Big Data Infrastructures |9 G:(DE-HGF)POF4-5122 |x 1 |
| 920 | _ | _ | |l yes |
| 920 | 1 | _ | |0 I:(DE-Juel1)PGI-4-20110106 |k PGI-4 |l Integrated Computing Architectures |x 0 |
| 920 | 1 | _ | |0 I:(DE-Juel1)JSC-20090406 |k JSC |l Jülich Supercomputing Center |x 1 |
| 980 | _ | _ | |a contrib |
| 980 | _ | _ | |a EDITORS |
| 980 | _ | _ | |a VDBINPRINT |
| 980 | _ | _ | |a contb |
| 980 | _ | _ | |a I:(DE-Juel1)PGI-4-20110106 |
| 980 | _ | _ | |a I:(DE-Juel1)JSC-20090406 |
| 980 | _ | _ | |a UNRESTRICTED |
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