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@INPROCEEDINGS{Krystofiak:1050052,
      author       = {Krystofiak, Lukas},
      title        = {{A} scaling-friendly memristor-based leaky
                      integrate-and-fire circuit in a {TSMC} 28nm process
                      technology},
      reportid     = {FZJ-2025-05766},
      year         = {2025},
      abstract     = {Spiking neural networks mimic the way the human brain
                      processes data and excel in efficiency. With the advent of
                      the memristor, foundations are laid for scalable and
                      low-power integrated electronic implementations. Key is the
                      small form factor of the memristor and its ability to
                      passively retain a multilevel state.To investigate the
                      feasibility of memristor-based spiking neural networks, a
                      first chip is developed containing all necessary circuits to
                      read and write memristors. It will be connected via
                      chip-to-chip bonding wires to a 3 by 3 memristor array. In
                      this abstract the focus is on the implemented leaky
                      integrate-and-fire circuit (LIF).While the memristors act as
                      the synapses of the neural network, the neurons are modeled
                      as current-based RC LIF circuits. Previous implementations
                      minimized the current to reduce the area footprint as much
                      as possible which is dominated by the capacitor size[1][2].
                      This is prone to process variations, especially in smaller
                      technology nodes. Thus, precise analog calibrations are
                      needed for every single neuron. This complicates scaling
                      spiking neuronal networks. A novel approach reduces the
                      width of incoming spikes in the LIF circuit to a fraction of
                      the original by an additional duty-cycle element which is
                      controlled by ɸPulse. This is generated globally by a
                      reference clock with an adjustable duty cycle and then
                      distributed to all LIF elements minimizing the wiring and
                      biasing overhead. Additionally, the operation time frame of
                      the SNN can be tuned through this. The duty cycle approach
                      effectively transforms the system to the time-discrete
                      domain, but with the very high switching speeds, enabled by
                      a 28 nm process technology, compared to the intended
                      operating speed of the neural network it can be regarded as
                      pseudo time-continuous.A first tapeout in a 28nm process
                      technology is scheduled for September 2025 and post-layout
                      simulations will be shown.},
      month         = {Oct},
      date          = {2025-10-13},
      organization  = {8th International Conference on
                       Memristive Materials, Devices $\&$
                       Systems, Edinburgh (UK), 13 Oct 2025 -
                       16 Oct 2025},
      subtyp        = {After Call},
      cin          = {PGI-4},
      cid          = {I:(DE-Juel1)PGI-4-20110106},
      pnm          = {5234 - Emerging NC Architectures (POF4-523)},
      pid          = {G:(DE-HGF)POF4-5234},
      typ          = {PUB:(DE-HGF)6},
      url          = {https://juser.fz-juelich.de/record/1050052},
}