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@ARTICLE{Zhao:1050093,
      author       = {Zhao, Qing-Tai and Han, Yi and Han, Hung-Chi and Schreiber,
                      Lars R. and Lee, Tsung-En and Chiang, Hung-Li and Radu,
                      Iuliana and Enz, Christian and Grützmacher, Detlev and
                      Stampfer, Christoph and Takagi, Shinichi and Knoch, Joachim},
      title        = {{U}ltra-low-power cryogenic complementary metal oxide
                      semiconductor technology},
      journal      = {Nature reviews / Electrical engineering},
      volume       = {2},
      number       = {4},
      issn         = {2948-1201},
      address      = {[London]},
      publisher    = {Nature Publishing Group UK},
      reportid     = {FZJ-2025-05801},
      pages        = {277 - 290},
      year         = {2025},
      abstract     = {Universal cryogenic computing, encompassing von Neumann,
                      neuromorphic and quantum computing, paves the way for future
                      big-data processing with high energy efficiency.
                      Complementary metal oxide semiconductor (CMOS) technology
                      operating at cryogenic temperatures with ultra-low power
                      consumption is a key component of this advancement. However,
                      classical CMOS technology, designed for room temperature
                      applications, suffers from band-tail effects at cryogenic
                      levels, leading to an increased subthreshold swing and
                      decreased mobility values. In addition, threshold voltages
                      are enlarged. Thus, classical CMOS technology fails to meet
                      the low power requirements when cooled close to zero Kelvin.
                      In this Perspective, we show that steep slope cryogenic
                      devices can be realized by screening the band tails with the
                      use of high-k dielectrics and wrap-gate architectures and/or
                      reducing them through the optimization of the surfaces and
                      interfaces within the transistors. Cryogenic device
                      functionality also strongly benefits from appropriate
                      source/drain engineering employing dopant segregation from
                      silicides. Furthermore, the threshold voltage control can be
                      realized with back-gating, work-function engineering and
                      dipole formation. As a major implication, future research
                      and development towards cryogenic CMOS technology requires a
                      combination of these approaches to enable universal
                      cryogenic computing at the necessary ultra-low power
                      levels.},
      cin          = {PGI-11 / PGI-9},
      cid          = {I:(DE-Juel1)PGI-11-20170113 / I:(DE-Juel1)PGI-9-20110106},
      pnm          = {5221 - Advanced Solid-State Qubits and Qubit Systems
                      (POF4-522)},
      pid          = {G:(DE-HGF)POF4-5221},
      typ          = {PUB:(DE-HGF)16},
      doi          = {10.1038/s44287-025-00157-7},
      url          = {https://juser.fz-juelich.de/record/1050093},
}