%0 Conference Paper
%A Manea, Paul-Philipp
%A Leroux, Nathan
%A Strachan, John Paul
%T Content Addressable Memory Hierarchies for Computing in Memory
%I IEEE
%M FZJ-2026-00229
%P 1-3
%D 2025
%< 2025 9th IEEE Electron Devices Technology & Manufacturing Conference (EDTM) : [Proceedings] - IEEE, 2025. - ISBN 979-8-3315-0416-8 - doi:10.1109/EDTM61175.2025.11040774
%X Content Addressable Memories (CAMs) match inputdata to stored content, ideal for search-intensive taskslike network address lookup and similarity matching.This paper explores CAM hierarchies (similar to thestandard RAM hierarchy), focusing on two implemen-tation layers: non-volatile, analog Content AddressableMemory (aCAM) for static data patterns, and volatile,gain cell-based aCAM for dynamic tasks. Mitigatingkey non-idealities in memristor-based aCAMs increasesstorage from 2 to 4 bits per cell, enhancing performance,capacity, and energy efficiency for Compute in Memory(CIM) applications.
%B 2025 9th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)
%C 9 Mar 2025 - 12 Mar 2025, Hong Kong (Hong Kong)
Y2 9 Mar 2025 - 12 Mar 2025
M2 Hong Kong, Hong Kong
%F PUB:(DE-HGF)8 ; PUB:(DE-HGF)7
%9 Contribution to a conference proceedingsContribution to a book
%R 10.1109/EDTM61175.2025.11040774
%U https://juser.fz-juelich.de/record/1050459