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024 7 _ |a 10.1109/EDTM61175.2025.11040774
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100 1 _ |a Manea, Paul-Philipp
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111 2 _ |a 2025 9th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)
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|d 2025-03-09 - 2025-03-12
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245 _ _ |a Content Addressable Memory Hierarchies for Computing in Memory
260 _ _ |c 2025
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295 1 0 |a 2025 9th IEEE Electron Devices Technology & Manufacturing Conference (EDTM) : [Proceedings] - IEEE, 2025. - ISBN 979-8-3315-0416-8 - doi:10.1109/EDTM61175.2025.11040774
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520 _ _ |a Content Addressable Memories (CAMs) match inputdata to stored content, ideal for search-intensive taskslike network address lookup and similarity matching.This paper explores CAM hierarchies (similar to thestandard RAM hierarchy), focusing on two implemen-tation layers: non-volatile, analog Content AddressableMemory (aCAM) for static data patterns, and volatile,gain cell-based aCAM for dynamic tasks. Mitigatingkey non-idealities in memristor-based aCAMs increasesstorage from 2 to 4 bits per cell, enhancing performance,capacity, and energy efficiency for Compute in Memory(CIM) applications.
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700 1 _ |a Leroux, Nathan
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700 1 _ |a Strachan, John Paul
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773 _ _ |a 10.1109/EDTM61175.2025.11040774
856 4 _ |u https://ieeexplore.ieee.org/abstract/document/11040774
856 4 _ |u https://juser.fz-juelich.de/record/1050459/files/Content_Addressable_Memory_Hierarchies_for_Computing_in_Memory.pdf
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