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@INPROCEEDINGS{Yang:1050575,
      author       = {Yang, Ming-Jay and Nieters, Pascal and Hellwig, Johannes
                      and Spithouris, Dimitrios and Dittmann, Regina and Pipa,
                      Gordon and Strachan, John Paul},
      title        = {{CMOS}-{M}emristive {D}endrite {A}rchitecture for
                      {R}eliable {T}emporal {P}attern {R}ecognition},
      reportid     = {FZJ-2026-00332},
      year         = {2025},
      abstract     = {Temporal sequences of spiking activity serve as a
                      fundamental medium through which the brain encodes and
                      processes information. Extracting meaningful temporal
                      structure from these sequences is a core computational task
                      for both biological and artificial intelligent systems1.
                      Recent advances in brain-inspired computing have introduced
                      the concept of dendritic plateau computation (DPC)—a
                      mechanism arising from the interaction of localized plateau
                      potentials across functionally compartmentalized dendritic
                      branches2,3. Inspired by this biological paradigm, we
                      propose a memristive dendritic architecture incorporating a
                      multi-compartmental neuron model. In this design, critical
                      temporal features are encoded through tunable resistances at
                      memristive crosspoints4, while the adjustable retention
                      times of volatile memristors5,6 are leveraged to implement
                      plateau durations, allowing temporal dynamics to be adapted
                      to application-specific requirements.We demonstrate that a
                      single neuron within this architecture achieves temporal
                      selectivity, even in the presence of timing variability.
                      Additionally, we construct a two-layer network of neuron
                      populations for sequence classification, a task complicated
                      by intra-sequence timing variation. Our results show that
                      the proposed memristive DPC hardware accurately classifies
                      temporal sequences without the need to store auxiliary
                      features for handling timing variability, thus reducing
                      network size and complexity. This work highlights the
                      potential of active dendritic processes as fundamental
                      computational primitives for realizing efficient,
                      brain-inspired hardware systems.},
      month         = {Oct},
      date          = {2025-10-13},
      organization  = {The 8th International Conference on
                       Memristive Materials, Devices $\&$
                       Systems (MEMRISYS 2025), Edinburgh
                       (United Kingdom), 13 Oct 2025 - 16 Oct
                       2025},
      subtyp        = {After Call},
      cin          = {PGI-14},
      cid          = {I:(DE-Juel1)PGI-14-20210412},
      pnm          = {5234 - Emerging NC Architectures (POF4-523)},
      pid          = {G:(DE-HGF)POF4-5234},
      typ          = {PUB:(DE-HGF)6},
      url          = {https://juser.fz-juelich.de/record/1050575},
}