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| Hauptseite > Publikationsdatenbank > A 28 nm PLL-Based Oscillator Network for Synchronization and Oscillator-based Optimization |
| Hauptseite > Publikationsdatenbank > A 28 nm PLL-Based Oscillator Network for Synchronization and Oscillator-based Optimization |
| Contribution to a conference proceedings | FZJ-2026-04984 |
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2026
IEEE
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Please use a persistent id in citations: doi:10.1109/SMACD70206.2026.11647793
Abstract: We present a coupled oscillator ASIC fabricated in 28 nm CMOS for high-speed exploration of synchronization dynamics and analog combinatorial optimization. Instead of relying on computationally intensive numerical simulations, the proposed architecture maps the Kuramoto phase interaction model onto the control dynamics of a cluster of third-order type-II Phase-Locked Loops (PLLs). The design employs ring-based Voltage Controlled Oscillators (VCOs) with programmable delay and coupling strength, enabling a scalable implementation without conventional RC interaction networks, whose passive coupling elements scale quadratically with network size. In contrast, inter-oscillator interactions are realized through digital logic, eliminating areaintensive passive hardware scaling while enabling dynamic control of coupling strength and delay. The fabricated prototype integrates seven PLL nodes operating in the 15.7−17.5 MHz range. Post-silicon measurements show a KVCO of 2.5−3.0 MHz/V and a frequency dispersion σ of 0.052-0.082 MHz, corresponding to an approximately 0.22 MHz 3σ mismatch manifold and an ∼8× frequency-pulling margin. Under strong coupling, the network exhibits stable phase-locked synchronization consistent with Kuramoto dynamics, demonstrating a scalable hardware platform for studying collective oscillator dynamics and oscillator-based optimization.
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