001     111886
005     20180211184739.0
024 7 _ |2 DOI
|a 10.1016/j.sse.2011.10.026
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|a Engineering, Electrical & Electronic
084 _ _ |2 WoS
|a Physics, Applied
084 _ _ |2 WoS
|a Physics, Condensed Matter
100 1 _ |a Knoll, L.
|b 0
|u FZJ
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245 _ _ |a 20 nm Gate length Schottky MOSFETs with ultra-thin NiSi/epitaxial NiSi2 source/drain
260 _ _ |a Oxford [u.a.]
|b Pergamon, Elsevier Science
|c 2012
300 _ _ |a 88 - 92
336 7 _ |a Journal Article
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440 _ 0 |a Solid-State Electronics
|x 0038-1101
|0 6634
|v 71
500 _ _ |3 POF3_Assignment on 2016-02-29
500 _ _ |a Record converted from VDB: 16.11.2012
520 _ _ |a Schottky barrier (SB)-MOSFETs with NiSi and epitaxial NiSi2 S/D contacts with gate lengths as small as 20 nm are presented. Epitaxial NiSi2 FETs show higher on-currents than corresponding NiSi devices due to its lower SB height. A striking observation is that tunnelling currents through the fairly large SB decrease at very short gate lengths in SB-MOSFETs, in contrast to the scaling behavior of conventional MOSFETs. Simulations indicate that the potential in the channel increases due to overlap of the high source and drain barriers with decreasing gate length, leading to lower currents. Boron implantation into the silicide (IIS) was used to lower the SBH. Devices with epitaxial NiSi2 show an improved performance after barrier lowering by (IIS). It is shown, that the parasitic potential increase of the two S/D Schottky barriers can be either minimized by IIS and by enhanced gate control due to EOT scaling using high-k as the gate oxide. (C) 2011 Elsevier Ltd. All rights reserved.
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|a Schottky-MOSFET
653 2 0 |2 Author
|a High-k
653 2 0 |2 Author
|a Scaling
653 2 0 |2 Author
|a NiSi
653 2 0 |2 Author
|a Epitaxial NiSi2
653 2 0 |2 Author
|a Short channel effects
653 2 0 |2 Author
|a Silicide source/drain
653 2 0 |2 Author
|a Implantation into silicide
653 2 0 |2 Author
|a Dopant segregation
700 1 _ |a Zhao, Q.T.
|b 1
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700 1 _ |a Lupták, R.
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700 1 _ |a Trellenkamp, S.
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700 1 _ |a Bourdelle, K.K.
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700 1 _ |a Mantl, S.
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773 _ _ |0 PERI:(DE-600)2012825-3
|a 10.1016/j.sse.2011.10.026
|g Vol. 71, p. 88 - 92
|p 88 - 92
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|t Solid state electronics
|v 71
|x 0038-1101
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856 7 _ |u http://dx.doi.org/10.1016/j.sse.2011.10.026
909 C O |o oai:juser.fz-juelich.de:111886
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