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@ARTICLE{Jovanovic:12008,
      author       = {Jovanovic, V. and Biasotto, C. and Nanver, L.K. and Moers,
                      J. and Grützmacher, D. and Gerharz, J. and Mussler, G. and
                      van der Cingel, J. and Zhang, J.J. and Bauer, G. and
                      Schmidt, O.G. and Miglio, L.},
      title        = {n-{C}hannel {MOSFET}s {F}abricated on {S}i{G}e {D}ots for
                      {S}train-{E}nhanced {M}obility},
      journal      = {IEEE Electron Device Letters},
      volume       = {31},
      issn         = {0741-3106},
      address      = {New York, NY},
      publisher    = {IEEE},
      reportid     = {PreJuSER-12008},
      pages        = {1083 - 1085},
      year         = {2010},
      note         = {This work was supported by the European Commission's Sixth
                      Framework Programme under the D-Dot FET project. The review
                      of this letter was arranged by Editor K. De Meyer.},
      abstract     = {The silicon germanium dots grown in the Stranski-Krastanow
                      mode are used to induce biaxial tensile strain in a silicon
                      capping layer. A high Ge content and correspondingly high Si
                      strain levels are reached due to the 3-D growth of the dots.
                      The n-channel MOS devices, referred to in this letter as
                      DotFETs, are processed with the main gate segment above the
                      strained Si layer on a single dot. To prevent the
                      intermixing of the Si/SiGe/Si structure, a novel
                      low-temperature FET structure processed below 400 degrees C
                      has been implemented: The ultrashallow source/drain
                      junctions formed by excimer-laser annealing in the full-melt
                      mode of ion-implanted dopants are self-aligned to a metal
                      gate. The crystallinity of the structure is preserved
                      throughout the processing, and compared to reference
                      devices, an average increase in the drain current of up to
                      $22.5\%$ is obtained.},
      keywords     = {J (WoSType)},
      cin          = {IBN-1 / JARA-FIT},
      ddc          = {620},
      cid          = {I:(DE-Juel1)VDB799 / $I:(DE-82)080009_20140620$},
      pnm          = {Grundlagen für zukünftige Informationstechnologien},
      pid          = {G:(DE-Juel1)FUEK412},
      shelfmark    = {Engineering, Electrical $\&$ Electronic},
      typ          = {PUB:(DE-HGF)16},
      UT           = {WOS:000283353900005},
      doi          = {10.1109/LED.2010.2058995},
      url          = {https://juser.fz-juelich.de/record/12008},
}