%0 Conference Paper
%A Kleines, Harald
%A Wüstner, Peter
%A Drochner, M.
%A Ackens, Axel
%A Erven, Wilhelm
%A Kämmerling, Peter
%A Ramm, M.
%A van Waasen, Stefan
%T Design of an Optical Uplink with 10 GBit/s between PCIe and MicroTCA
%M FZJ-2013-00666
%D 2012
%X In the context of developments for the PANDA detector system an optical uplink from MicroTCA to PCIe is under development. The uplink is based on X2 transceivers with a nominal speed of 10 GBit/s. The PCIe board has already been produced and it is currently under test. It is based on a Xilinx Virtex 5 (XC5VLX30T) FPGA. For the implementation of the XAUI interface to the X2 transceiver a PM8358 SERDES with a parallel interface to the FPGA is used. The corresponding AMC module is based on the same components. Open issues regarding the  FPGA implementation of the link protocol will be discussed.
%B 18th IEEE Real Time Conference
%C 11 Jun 2012 - 15 Jun 2012, Berkeley (USA)
Y2 11 Jun 2012 - 15 Jun 2012
M2 Berkeley, USA
%F PUB:(DE-HGF)24
%9 Poster
%U https://juser.fz-juelich.de/record/129146