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001     129146
005     20250129092453.0
037 _ _ |a FZJ-2013-00666
100 1 _ |a Kleines, Harald
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111 2 _ |a 18th IEEE Real Time Conference
|w USA
|c Berkeley
|d 2012-06-11 - 2012-06-15
|g IEEE RT2012
245 _ _ |a Design of an Optical Uplink with 10 GBit/s between PCIe and MicroTCA
260 _ _ |c 2012
336 7 _ |a Poster
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336 7 _ |a INPROCEEDINGS
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520 _ _ |a In the context of developments for the PANDA detector system an optical uplink from MicroTCA to PCIe is under development. The uplink is based on X2 transceivers with a nominal speed of 10 GBit/s. The PCIe board has already been produced and it is currently under test. It is based on a Xilinx Virtex 5 (XC5VLX30T) FPGA. For the implementation of the XAUI interface to the X2 transceiver a PM8358 SERDES with a parallel interface to the FPGA is used. The corresponding AMC module is based on the same components. Open issues regarding the FPGA implementation of the link protocol will be discussed.
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700 1 _ |a Wüstner, Peter
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700 1 _ |a Drochner, M.
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700 1 _ |a Ackens, Axel
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700 1 _ |a Erven, Wilhelm
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700 1 _ |a Kämmerling, Peter
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700 1 _ |a Ramm, M.
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700 1 _ |a van Waasen, Stefan
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909 C O |o oai:juser.fz-juelich.de:129146
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910 1 _ |a Zentralinstitut für Elektronik
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