000135255 001__ 135255
000135255 005__ 20250129092433.0
000135255 037__ $$aFZJ-2013-03210
000135255 041__ $$aEnglish
000135255 1001_ $$0P:(DE-Juel1)156521$$aKruth, Andre$$b0$$eCorresponding author
000135255 1112_ $$aTopical Workshop on Electronics for Particle Physics$$cParis$$d21092009 - 25092009$$gTWEEP-09$$wFrance
000135255 245__ $$aCharge Pump Clock Generation PLL for the Data Output Blocks of the Upgraded ATLAS Front-End in 130nm CMOS
000135255 260__ $$c2009
000135255 300__ $$a?
000135255 3367_ $$0PUB:(DE-HGF)8$$2PUB:(DE-HGF)$$aContribution to a conference proceedings$$bcontrib$$mcontrib$$s1375694181_27418
000135255 3367_ $$033$$2EndNote$$aConference Paper
000135255 3367_ $$2ORCID$$aCONFERENCE_PAPER
000135255 3367_ $$2DataCite$$aOutput Types/Conference Paper
000135255 3367_ $$2DRIVER$$aconferenceObject
000135255 3367_ $$2BibTeX$$aINPROCEEDINGS
000135255 520__ $$aFE-I4 is the 130 nm ATLAS pixel IC currently under development for upgraded Large Hadron Collider (LHC) luminosities. FE-I4 is based on a low-power analog pixel array and digital architecture concepts tuned to higher hit rates [1]. An integrated Phase Locked Loop (PLL) has been developed that locally generates a clock signal for the 160 Mbit/s output data stream from the 40 MHz bunch crossing reference clock. This block is designed for low power, low area consumption and recovers quickly from loss of lock related to single-event transients in the high radiation environment of the ATLAS pixel detector. After a general introduction to the new FE-I4 pixel front-end chip, this work focuses on the FE-I4 output blocks and on a first PLL prototype test chip submitted in early 2009. The PLL is nominally operated from a 1.2V supply and consumes 3.84mW of DC power. Under nominal operating conditions, the control voltage settles to within 2% of its nominal value in less than 700 ns. The nominal operating frequency for the ring-oscillator based Voltage Controlled Oscillator (VCO) is fVCO = 640MHz. The last sections deal with a fabricated demonstrator that provides the option of feeding the single-ended 80MHz output clock of the PLL as a clock signal to a digital test logic block integrated on-chip. The digital logic consists of an eight bit pseudo-random binary sequence generator, an eight bit to ten bit coder and a serializer. It processes data with a speed of 160 Mbit/s. All dynamic signals are driven off-chip by custommade pseudo-LVDS drivers.
000135255 536__ $$0G:(DE-HGF)POF2-899$$a899 - ohne Topic (POF2-899)$$cPOF2-899$$fPOF I$$x0
000135255 8564_ $$uhttp://indico.cern.ch/getFile.py/access?contribId=35&sessionId=30&resId=0&materialId=paper&confId=49682
000135255 909CO $$ooai:juser.fz-juelich.de:135255$$pVDB
000135255 9101_ $$0I:(DE-Juel1)ZEA-2-20090406$$6P:(DE-Juel1)156521$$aZentralinstitut für Elektronik$$b0$$kZEA-2
000135255 9131_ $$0G:(DE-HGF)POF2-899$$1G:(DE-HGF)POF2-890$$2G:(DE-HGF)POF2-800$$3G:(DE-HGF)POF2$$4G:(DE-HGF)POF$$aDE-HGF$$bProgrammungebundene Forschung$$lohne Programm$$vohne Topic$$x0
000135255 9141_ $$y2013
000135255 920__ $$lyes
000135255 9201_ $$0I:(DE-Juel1)ZEA-2-20090406$$kZEA-2$$lZentralinstitut für Elektronik$$x0
000135255 980__ $$acontrib
000135255 980__ $$aVDB
000135255 980__ $$aUNRESTRICTED
000135255 980__ $$aI:(DE-Juel1)ZEA-2-20090406
000135255 981__ $$aI:(DE-Juel1)PGI-4-20110106