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@INPROCEEDINGS{Kruth:135255,
      author       = {Kruth, Andre},
      title        = {{C}harge {P}ump {C}lock {G}eneration {PLL} for the {D}ata
                      {O}utput {B}locks of the {U}pgraded {ATLAS} {F}ront-{E}nd in
                      130nm {CMOS}},
      reportid     = {FZJ-2013-03210},
      pages        = {?},
      year         = {2009},
      abstract     = {FE-I4 is the 130 nm ATLAS pixel IC currently under
                      development for upgraded Large Hadron Collider (LHC)
                      luminosities. FE-I4 is based on a low-power analog pixel
                      array and digital architecture concepts tuned to higher hit
                      rates [1]. An integrated Phase Locked Loop (PLL) has been
                      developed that locally generates a clock signal for the 160
                      Mbit/s output data stream from the 40 MHz bunch crossing
                      reference clock. This block is designed for low power, low
                      area consumption and recovers quickly from loss of lock
                      related to single-event transients in the high radiation
                      environment of the ATLAS pixel detector. After a general
                      introduction to the new FE-I4 pixel front-end chip, this
                      work focuses on the FE-I4 output blocks and on a first PLL
                      prototype test chip submitted in early 2009. The PLL is
                      nominally operated from a 1.2V supply and consumes 3.84mW of
                      DC power. Under nominal operating conditions, the control
                      voltage settles to within $2\%$ of its nominal value in less
                      than 700 ns. The nominal operating frequency for the
                      ring-oscillator based Voltage Controlled Oscillator (VCO) is
                      fVCO = 640MHz. The last sections deal with a fabricated
                      demonstrator that provides the option of feeding the
                      single-ended 80MHz output clock of the PLL as a clock signal
                      to a digital test logic block integrated on-chip. The
                      digital logic consists of an eight bit pseudo-random binary
                      sequence generator, an eight bit to ten bit coder and a
                      serializer. It processes data with a speed of 160 Mbit/s.
                      All dynamic signals are driven off-chip by custommade
                      pseudo-LVDS drivers.},
      date          = {21092009},
      organization  = {Topical Workshop on Electronics for
                       Particle Physics, Paris (France),
                       21092009 - 25092009},
      cin          = {ZEA-2},
      cid          = {I:(DE-Juel1)ZEA-2-20090406},
      pnm          = {899 - ohne Topic (POF2-899)},
      pid          = {G:(DE-HGF)POF2-899},
      typ          = {PUB:(DE-HGF)8},
      url          = {https://juser.fz-juelich.de/record/135255},
}