Thin film high permittivity materials such as perovskite-type mixed oxide insulators are promising candidates to replace SiO₂SiN_x. in future ultra-large-scale integrated Gbit-DRAM chips, e.g. as dielectric in capacitors of memory cells or as gate oxide in MOSFETs. As too high leakage currents are a big concern we have performed systematic experimental studies on leakage currents through metal/insulator/metal (MIM) planar capacitors us-ing high permittivity alloys such as SrTiO₃ (STO) and (Ba_xSr_1-x)TiO₃ (BST) as thin film dielectrics and a wide variation of external parameters (dielectric thickness, applied field and temperature, etc.). We also have used a new approach for describing the electronic transport through the insulator and performed finite difference simu-lation studies with this newly developed model. The main results are reported showing good agreement be-tween the experimental and simulation data, indicating that the leakage currents in these materials with low electronic mobility are film "bulk" limited, in contrast to the often postulated interface ("Schottky-barrier") limitation.