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@PHDTHESIS{Nichau:139691,
      author       = {Nichau, Alexander},
      title        = {{C}haracterization, integration and reliability of
                      {H}f{O}$_2$ and {L}a{L}u{O}$_3$ high-$\kappa$/metal gate
                      stacks for {CMOS} applications},
      volume       = {28},
      school       = {RWTH Aachen},
      type         = {Dr.},
      address      = {Jülich},
      publisher    = {Forschungszentrum Jülich GmbH Zentralbibliothek, Verlag},
      reportid     = {FZJ-2013-05665},
      isbn         = {978-3-89336-898-3},
      series       = {Schriften des Forschungszetrum Jülich. Reihe Information /
                      information},
      pages        = {177 S.},
      year         = {2013},
      note         = {RWTH Aachen, Diss., 2013},
      abstract     = {The continued downscaling of MOSFET dimensions requires an
                      equivalent oxide thickness (EOT) of the gate stack below 1
                      nm. An EOT below 1.4 nm is hereby enabled by the use of
                      high-$\kappa$/metal gate stacks. LaLuO$_{3}$ and HfO$_{2}$
                      are investigated as two different high-$\kappa$ oxides on
                      silicon in conjunction with TiN as the metal electrode.
                      LaLuO$_{3}$ and its temperature-dependent silicate formation
                      are characterized by hard X-ray photoemission spectroscopy
                      (HAXPES). The effective attenuation length of LaLuO$_{3}$ is
                      determined between 7 and 13 keV to enable future interface
                      and diffusion studies. In a first investigation of
                      LaLuO$_{3}$ on germanium, germanate formation is shown.
                      LaLuO$_{3}$ is further integrated in a high-temperature
                      MOSFET process flow with varying thermal treatment. The
                      devices feature drive currents up to 70µA/µm at 1µm gate
                      length. Several optimization steps are presented. The
                      effective device mobility is related to silicate formation
                      and thermal budget. At high temperature the silicate
                      formation leads to mobility degradation due to La-rich
                      silicate formation. The integration of LaLuO$_{3}$ in high-T
                      processes delicately connects with the optimization of the
                      TiN metal electrode. Hereby, stoichiometric TiN yields the
                      best results in terms of thermal stability with respect to
                      Si-capping and high$\kappa$ oxide. Different approaches are
                      presented for a further EOT reduction with LaLuO$_{3}$ and
                      HfO$_{2}$. Thereby the thermodynamic and kinetic predictions
                      are employed to estimate the behavior on the nanoscale.
                      Based on thermodynamics, excess oxygen in the gate stack,
                      especially in oxidized metal electrodes, is identified to
                      prevent EOT scaling below 1.2 nm. The equivalent oxide
                      thickness of HfO$_{2}$ gate stacks is scalable below 1 nm by
                      the use of thinned interfacial SiO$_{2}$. The prevention of
                      oxygen incorporation into the metal electrode by Si-capping
                      maintains the EOT after high temperature annealing. Redox
                      systems are employed within the gate electrode to decrease
                      the EOT of HfO$_{2}$ gate stacks. A lower limit found was
                      EOT=5 Å for Al doping inside TiN. The doping of TiN on
                      LaLuO$_{3}$ is proven by electron energy loss spectroscopy
                      (EELS) studies to modify the interfacial silicate layer to
                      La-rich silicates or even reduce the layer. The oxide
                      quality in Si/HfO$_{2}$/TiN gate stacks is characterized by
                      charge pumping and carrier mobility measurements on 3d
                      MOSFETs a.k.a. FinFETs. The oxide quality in terms of the
                      number of interface (and oxide) traps on top- and sidewall
                      of FinFETs is compared for three different annealing
                      processes. A high temperature anneal of HfO$_{2}$ improves
                      significantly the oxide quality and mobility. The gate oxide
                      integrity (GOI) of gate stacks below 1 nm EOT is determined
                      by time-dependent dielectric breakdown (TDDB) measurements
                      on FinFETs with HfO$_{2}$/TiN gate stacks. A successful EOT
                      scaling has always to consider the oxide quality and
                      resulting reliability. Degraded oxide quality leads to
                      mobility degradation and earlier soft-breakdown, i.e.
                      leakage current increase.},
      keywords     = {Dissertation (GND)},
      cin          = {PGI-9 / JARA-FIT},
      cid          = {I:(DE-Juel1)PGI-9-20110106 / $I:(DE-82)080009_20140620$},
      pnm          = {421 - Frontiers of charge based Electronics (POF2-421)},
      pid          = {G:(DE-HGF)POF2-421},
      typ          = {PUB:(DE-HGF)11},
      urn          = {urn:nbn:de:hbz:82-opus-47289},
      url          = {https://juser.fz-juelich.de/record/139691},
}