TY  - CONF
AU  - Knoll, Lars
AU  - Zhao, Qing-Tai
AU  - Nichau, Alexander
AU  - Richter, Simon
AU  - Luong, Gia Vinh
AU  - Trellenkamp, Stefan
AU  - Schäfer, Anna
AU  - Selmi, Luca
AU  - Bourdelle, K. K.
AU  - Mantl, Siegfried
TI  - Demonstration of Improved Transient Response of Inverters with Steep Slope Strained Si NW TFETs by Reduction of TAT with Pulsed I-V and NW Scaling
PB  - IEEE
M1  - FZJ-2013-06673
SN  - 978-1-4799-2307-6
SP  - 100-103
PY  - 2013
AB  - We present gate all around strained Si (sSi) nanowire array TFETs with high ION (64μA/μm at VDD=1.0V). Pulsed I-V measurements provide small SS and record I60 of 1×10-2μA/μm at 300K due to the suppression of  trap assisted tunneling (TAT). Scaling the nanowires to 10 nm diameter greatly suppresses the impact of TAT and improves SS and ION. Transient analysis of complementary TFET inverters demonstrates experimentally for the first time that device scaling and improved electrostatics yields to faster time response.
T2  - International Electron Device Meeting
CY  - 9 Dec 2013 - 11 Dec 2013, Washington DC (USA)
Y2  - 9 Dec 2013 - 11 Dec 2013
M2  - Washington DC, USA
LB  - PUB:(DE-HGF)8 ; PUB:(DE-HGF)7
UR  - https://juser.fz-juelich.de/record/141505
ER  -