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| Hauptseite > Publikationsdatenbank > Demonstration of Improved Transient Response of Inverters with Steep Slope Strained Si NW TFETs by Reduction of TAT with Pulsed I-V and NW Scaling > print |
| Hauptseite > Publikationsdatenbank > Demonstration of Improved Transient Response of Inverters with Steep Slope Strained Si NW TFETs by Reduction of TAT with Pulsed I-V and NW Scaling > print |
| 001 | 141505 | ||
| 005 | 20210129213000.0 | ||
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| 100 | 1 | _ | |0 P:(DE-Juel1)162211 |a Knoll, Lars |b 0 |e Corresponding author |u fzj |
| 111 | 2 | _ | |a International Electron Device Meeting |c Washington DC |d 2013-12-09 - 2013-12-11 |w USA |
| 245 | _ | _ | |a Demonstration of Improved Transient Response of Inverters with Steep Slope Strained Si NW TFETs by Reduction of TAT with Pulsed I-V and NW Scaling |
| 260 | _ | _ | |b IEEE |c 2013 |
| 295 | 1 | 0 | |a IEDM Technical Digest 2013 |
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| 520 | _ | _ | |a We present gate all around strained Si (sSi) nanowire array TFETs with high ION (64μA/μm at VDD=1.0V). Pulsed I-V measurements provide small SS and record I60 of 1×10-2μA/μm at 300K due to the suppression of trap assisted tunneling (TAT). Scaling the nanowires to 10 nm diameter greatly suppresses the impact of TAT and improves SS and ION. Transient analysis of complementary TFET inverters demonstrates experimentally for the first time that device scaling and improved electrostatics yields to faster time response. |
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