TY  - JOUR
AU  - Durgun Özben, E.
AU  - Lopes, J.M.J.
AU  - Nichau, A.
AU  - Schnee, M.
AU  - Lenk, S.
AU  - Besmehn, A.
AU  - Bourdelle, K.K.
AU  - Zhao, Q.T.
AU  - Schubert, J.
AU  - Mantl, S.
TI  - Integration of LaLuO3 (k 30) as High-k Dielectric on Strained and Unstrained SOI MOSFETs with Replacement Gate Process
JO  - IEEE Electron Device Letters
VL  - 32
SN  - 0741-3106
CY  - New York, NY
PB  - IEEE
M1  - PreJuSER-14180
SP  - 15 - 17
PY  - 2011
N1  - This work was supported in part by the Project KZWEI which is funded in line with the technology funding for regional development (ERDF) of the European Union and by funds of the Free State of Saxony, by the German Federal Ministry of Education and Research through the MEDEA+ project DECISIF under Grant 2T104, and by the Nanosil network from the European Community under FP7 Grant 216171. The review of this letter was arranged by Editor J. Cai.
AB  - The integration of lanthanum lutetium oxide (LaLuO3) with a kappa value of 30 is, for the first time, demonstrated on strained and unstrained SOI n/p-MOSFETs as a gate dielectric with a full replacement gate process. The LaLuO3/Si interface showed a very thin silicate/SiO2 interlayer with a D-it level of 4.5 x 10(11) (eV . cm(2))(-1). Fully depleted n/p-MOSFETs with LaLuO3/TiN gate stacks indicated very good performance with steep subthreshold slopes of similar to 70 mV/dec and high I-on/I-off ratios. In addition, strained SOI shows enhanced electron mobilities with a factor of 1.7 compared to SOI. Both electron and hole mobilities for LaLuO3 on SOI are similar to the mobilities in reported Hf-based high-kappa devices.
KW  - J (WoSType)
LB  - PUB:(DE-HGF)16
UR  - <Go to ISI:>//WOS:000285844400005
DO  - DOI:10.1109/LED.2010.2089423
UR  - https://juser.fz-juelich.de/record/14180
ER  -