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@ARTICLE{Durgunzben:14180,
      author       = {Durgun Özben, E. and Lopes, J.M.J. and Nichau, A. and
                      Schnee, M. and Lenk, S. and Besmehn, A. and Bourdelle, K.K.
                      and Zhao, Q.T. and Schubert, J. and Mantl, S.},
      title        = {{I}ntegration of {L}a{L}u{O}3 (k 30) as {H}igh-k
                      {D}ielectric on {S}trained and {U}nstrained {SOI} {MOSFET}s
                      with {R}eplacement {G}ate {P}rocess},
      journal      = {IEEE Electron Device Letters},
      volume       = {32},
      issn         = {0741-3106},
      address      = {New York, NY},
      publisher    = {IEEE},
      reportid     = {PreJuSER-14180},
      pages        = {15 - 17},
      year         = {2011},
      note         = {This work was supported in part by the Project KZWEI which
                      is funded in line with the technology funding for regional
                      development (ERDF) of the European Union and by funds of the
                      Free State of Saxony, by the German Federal Ministry of
                      Education and Research through the MEDEA+ project DECISIF
                      under Grant 2T104, and by the Nanosil network from the
                      European Community under FP7 Grant 216171. The review of
                      this letter was arranged by Editor J. Cai.},
      abstract     = {The integration of lanthanum lutetium oxide (LaLuO3) with a
                      kappa value of 30 is, for the first time, demonstrated on
                      strained and unstrained SOI n/p-MOSFETs as a gate dielectric
                      with a full replacement gate process. The LaLuO3/Si
                      interface showed a very thin silicate/SiO2 interlayer with a
                      D-it level of 4.5 x 10(11) (eV . cm(2))(-1). Fully depleted
                      n/p-MOSFETs with LaLuO3/TiN gate stacks indicated very good
                      performance with steep subthreshold slopes of similar to 70
                      mV/dec and high I-on/I-off ratios. In addition, strained SOI
                      shows enhanced electron mobilities with a factor of 1.7
                      compared to SOI. Both electron and hole mobilities for
                      LaLuO3 on SOI are similar to the mobilities in reported
                      Hf-based high-kappa devices.},
      keywords     = {J (WoSType)},
      cin          = {PGI-9 / ZCH / JARA-FIT},
      ddc          = {620},
      cid          = {I:(DE-Juel1)PGI-9-20110106 / I:(DE-Juel1)ZCH-20090406 /
                      $I:(DE-82)080009_20140620$},
      pnm          = {Grundlagen für zukünftige Informationstechnologien /
                      NANOSIL - Silicon-based nanostructures and nanodevices for
                      long term nanoelectronics applications (216171)},
      pid          = {G:(DE-Juel1)FUEK412 / G:(EU-Grant)216171},
      shelfmark    = {Engineering, Electrical $\&$ Electronic},
      typ          = {PUB:(DE-HGF)16},
      UT           = {WOS:000285844400005},
      doi          = {10.1109/LED.2010.2089423},
      url          = {https://juser.fz-juelich.de/record/14180},
}