%0 Conference Proceedings
%A Kleines, Harald
%A Wustner, Peter
%A Drochner, Matthias
%A Ackens, Axel
%A Erven, Wilhelm
%A Kammerling, Peter
%A Ramm, Michael
%A van Waasen, Stefan
%T Design of an optical uplink with 10 GBit/s between PCIe and MicroTCA
%I IEEE
%M FZJ-2014-01174
%D 2012
%X In the context of developments for the PANDA detector system an optical uplink from MicroTCA to PCIe is under development. The uplink is based on X2 transceivers with a nominal speed of 10 GBit/s. The PCIe board has already been produced and it is currently under test. It is based on a Xilinx Virtex 5 (XC5VLX30T) FPGA. For the implementation of the XAUI interface to the X2 transceiver a PM8358 SERDES with a parallel interface to the FPGA is used. The corresponding AMC module is based on the same components. Open issues regarding the FPGA implementation of the link protocol will be discussed.
%B 2012 IEEE-NPSS Real Time Conference (RT 2012)
%C 9 Jun 2012 - 15 Jun 2012, Berkeley (CA)
Y2 9 Jun 2012 - 15 Jun 2012
M2 Berkeley, CA
%F PUB:(DE-HGF)26
%9 Proceedings
%R 10.1109/RTC.2012.6418149
%U https://juser.fz-juelich.de/record/151175