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000151175 0247_ $$2doi$$a10.1109/RTC.2012.6418149
000151175 037__ $$aFZJ-2014-01174
000151175 1001_ $$0P:(DE-Juel1)133905$$aKleines, Harald$$b0$$eCorresponding author
000151175 1112_ $$a2012 IEEE-NPSS Real Time Conference (RT 2012)$$cBerkeley$$d2012-06-09 - 2012-06-15$$wCA
000151175 245__ $$aDesign of an optical uplink with 10 GBit/s between PCIe and MicroTCA
000151175 260__ $$bIEEE$$c2012
000151175 3367_ $$0PUB:(DE-HGF)26$$2PUB:(DE-HGF)$$aProceedings$$bproc$$mproc$$s1406893077_27351
000151175 3367_ $$2BibTeX$$aPROCEEDINGS
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000151175 520__ $$aIn the context of developments for the PANDA detector system an optical uplink from MicroTCA to PCIe is under development. The uplink is based on X2 transceivers with a nominal speed of 10 GBit/s. The PCIe board has already been produced and it is currently under test. It is based on a Xilinx Virtex 5 (XC5VLX30T) FPGA. For the implementation of the XAUI interface to the X2 transceiver a PM8358 SERDES with a parallel interface to the FPGA is used. The corresponding AMC module is based on the same components. Open issues regarding the FPGA implementation of the link protocol will be discussed.
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000151175 7001_ $$0P:(DE-Juel1)133959$$aWustner, Peter$$b1
000151175 7001_ $$0P:(DE-HGF)0$$aDrochner, Matthias$$b2
000151175 7001_ $$0P:(DE-Juel1)133859$$aAckens, Axel$$b3
000151175 7001_ $$0P:(DE-Juel1)133883$$aErven, Wilhelm$$b4
000151175 7001_ $$0P:(DE-Juel1)133909$$aKammerling, Peter$$b5
000151175 7001_ $$0P:(DE-HGF)0$$aRamm, Michael$$b6
000151175 7001_ $$0P:(DE-Juel1)142562$$avan Waasen, Stefan$$b7
000151175 773__ $$a10.1109/RTC.2012.6418149$$y2012
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000151175 9101_ $$0I:(DE-Juel1)ZEA-2-20090406$$6P:(DE-Juel1)133905$$aZentralinstitut für Elektronik$$b0$$kZEA-2
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