TY  - CONF
AU  - Kleines, Harald
AU  - Wustner, Peter
AU  - Drochner, Matthias
AU  - Ackens, Axel
AU  - Erven, Wilhelm
AU  - Kammerling, Peter
AU  - Ramm, Michael
AU  - van Waasen, Stefan
TI  - Design of an optical uplink with 10 GBit/s between PCIe and MicroTCA
PB  - IEEE
M1  - FZJ-2014-01174
PY  - 2012
AB  - In the context of developments for the PANDA detector system an optical uplink from MicroTCA to PCIe is under development. The uplink is based on X2 transceivers with a nominal speed of 10 GBit/s. The PCIe board has already been produced and it is currently under test. It is based on a Xilinx Virtex 5 (XC5VLX30T) FPGA. For the implementation of the XAUI interface to the X2 transceiver a PM8358 SERDES with a parallel interface to the FPGA is used. The corresponding AMC module is based on the same components. Open issues regarding the FPGA implementation of the link protocol will be discussed.
T2  - 2012 IEEE-NPSS Real Time Conference (RT 2012)
CY  - 9 Jun 2012 - 15 Jun 2012, Berkeley (CA)
Y2  - 9 Jun 2012 - 15 Jun 2012
M2  - Berkeley, CA
LB  - PUB:(DE-HGF)26
DO  - DOI:10.1109/RTC.2012.6418149
UR  - https://juser.fz-juelich.de/record/151175
ER  -