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@PROCEEDINGS{Kleines:151175,
      author       = {Kleines, Harald and Wustner, Peter and Drochner, Matthias
                      and Ackens, Axel and Erven, Wilhelm and Kammerling, Peter
                      and Ramm, Michael and van Waasen, Stefan},
      title        = {{D}esign of an optical uplink with 10 {GB}it/s between
                      {PCI}e and {M}icro{TCA}},
      publisher    = {IEEE},
      reportid     = {FZJ-2014-01174},
      year         = {2012},
      abstract     = {In the context of developments for the PANDA detector
                      system an optical uplink from MicroTCA to PCIe is under
                      development. The uplink is based on X2 transceivers with a
                      nominal speed of 10 GBit/s. The PCIe board has already been
                      produced and it is currently under test. It is based on a
                      Xilinx Virtex 5 (XC5VLX30T) FPGA. For the implementation of
                      the XAUI interface to the X2 transceiver a PM8358 SERDES
                      with a parallel interface to the FPGA is used. The
                      corresponding AMC module is based on the same components.
                      Open issues regarding the FPGA implementation of the link
                      protocol will be discussed.},
      month         = {Jun},
      date          = {2012-06-09},
      organization  = {2012 IEEE-NPSS Real Time Conference
                       (RT 2012), Berkeley (CA), 9 Jun 2012 -
                       15 Jun 2012},
      cin          = {ZEA-2},
      cid          = {I:(DE-Juel1)ZEA-2-20090406},
      pnm          = {53G - COSY (POF2-53G32)},
      pid          = {G:(DE-HGF)POF2-53G32},
      typ          = {PUB:(DE-HGF)26},
      doi          = {10.1109/RTC.2012.6418149},
      url          = {https://juser.fz-juelich.de/record/151175},
}