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@INPROCEEDINGS{Durini:153873,
      author       = {Durini, Daniel and Weyers, Sascha and Goehlich, Andreas and
                      Brockherde, Werner and Paschen, Uwe and Vogt, Holger and
                      Federica, Villa and Bronzi, Danilo and Tisa, Simone and
                      Tosi, Alberto and Zappa, Franco},
      title        = {{CMOS} {T}echnology for {SPAD} / {S}i{PM}: {R}esults from
                      the {M}i{SP}i{A} {P}roject},
      reportid     = {FZJ-2014-03352},
      year         = {2014},
      abstract     = {Many demanding applications require single-photon detectors
                      with very large active area, very low noise, high detection
                      efficiency, and precise time response. Single-photon
                      avalanche diodes (SPADs) provide all the advantages of
                      solid-state devices, but in many applications other
                      single-photon detectors, like photomultiplier tubes, have
                      been preferred so far due to their larger active area. We
                      developed silicon SPADs with active area diameters as large
                      as 500 µm in a fully standard CMOS process. The 500 µm
                      SPAD exhibits $55\%$ peak photon detection efficiency at 420
                      nm, 8 kcps of dark counting rate at 0°C, and high
                      uniformity of the sensitivity in the active area. These
                      devices can be used with on-chip integrated quenching
                      circuitry, which reduces the afterpulsing probability, or
                      with external ciruits to achieve even better photon-timing
                      performances, as good as 92 ps FWHM for a 100 µm diameter
                      SPAD. Owing to the state-of-the-art performance, not only
                      compared to the CMOS SPADs but also SPADs developed in
                      custom technologies, very high uniformity and low cros-talk
                      probability, these CMOS SPADs can be succesfully employed in
                      detector arrays and single-chip imagers for single-photon
                      counting and timing applications. In order to solve the CMOS
                      SPAD fill-factor problems, back-side illuminated SPAD
                      (BackSPAD) technology was developed based on a 0.35 µm
                      SOI-CMOS process, where the wafer containing readout
                      circuitry fabricated in a standard CMOS technology is
                      flip-bonded on top of the detector array SOI-wafer, the
                      handle-wafer of which is then completely removed to enable
                      back-side illumination.},
      month         = {May},
      date          = {2014-05-20},
      organization  = {7th Fraunhofer IMS Workshop "CMOS
                       Imaging: From Photon to Camera",
                       Duisburg, Germany, May 20-21, 2014,
                       Duisburg (Germany), 20 May 2014 - 21
                       May 2014},
      subtyp        = {Invited},
      cin          = {ZEA-2},
      cid          = {I:(DE-Juel1)ZEA-2-20090406},
      pnm          = {434 - Optics and Photonics (POF2-434) / 423 - Sensorics and
                      bioinspired systems (POF2-423)},
      pid          = {G:(DE-HGF)POF2-434 / G:(DE-HGF)POF2-423},
      typ          = {PUB:(DE-HGF)6},
      url          = {https://juser.fz-juelich.de/record/153873},
}