Hauptseite > Publikationsdatenbank > CMOS Technology for SPAD / SiPM: Results from the MiSPiA Project > print |
001 | 153873 | ||
005 | 20250129092455.0 | ||
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037 | _ | _ | |a FZJ-2014-03352 |
041 | _ | _ | |a English |
100 | 1 | _ | |a Durini, Daniel |0 P:(DE-Juel1)161528 |b 0 |e Corresponding Author |u fzj |
111 | 2 | _ | |a 7th Fraunhofer IMS Workshop "CMOS Imaging: From Photon to Camera", Duisburg, Germany, May 20-21, 2014 |g IMS CMOS Imaging Workshop |c Duisburg |d 2014-05-20 - 2014-05-21 |w Germany |
245 | _ | _ | |a CMOS Technology for SPAD / SiPM: Results from the MiSPiA Project |
260 | _ | _ | |c 2014 |
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336 | 7 | _ | |a Conference Paper |0 33 |2 EndNote |
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336 | 7 | _ | |a INPROCEEDINGS |2 BibTeX |
520 | _ | _ | |a Many demanding applications require single-photon detectors with very large active area, very low noise, high detection efficiency, and precise time response. Single-photon avalanche diodes (SPADs) provide all the advantages of solid-state devices, but in many applications other single-photon detectors, like photomultiplier tubes, have been preferred so far due to their larger active area. We developed silicon SPADs with active area diameters as large as 500 µm in a fully standard CMOS process. The 500 µm SPAD exhibits 55% peak photon detection efficiency at 420 nm, 8 kcps of dark counting rate at 0°C, and high uniformity of the sensitivity in the active area. These devices can be used with on-chip integrated quenching circuitry, which reduces the afterpulsing probability, or with external ciruits to achieve even better photon-timing performances, as good as 92 ps FWHM for a 100 µm diameter SPAD. Owing to the state-of-the-art performance, not only compared to the CMOS SPADs but also SPADs developed in custom technologies, very high uniformity and low cros-talk probability, these CMOS SPADs can be succesfully employed in detector arrays and single-chip imagers for single-photon counting and timing applications. In order to solve the CMOS SPAD fill-factor problems, back-side illuminated SPAD (BackSPAD) technology was developed based on a 0.35 µm SOI-CMOS process, where the wafer containing readout circuitry fabricated in a standard CMOS technology is flip-bonded on top of the detector array SOI-wafer, the handle-wafer of which is then completely removed to enable back-side illumination. |
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536 | _ | _ | |a 423 - Sensorics and bioinspired systems (POF2-423) |0 G:(DE-HGF)POF2-423 |c POF2-423 |f POF II |x 1 |
700 | 1 | _ | |a Weyers, Sascha |0 P:(DE-HGF)0 |b 1 |
700 | 1 | _ | |a Goehlich, Andreas |0 P:(DE-HGF)0 |b 2 |
700 | 1 | _ | |a Brockherde, Werner |0 P:(DE-HGF)0 |b 3 |
700 | 1 | _ | |a Paschen, Uwe |0 P:(DE-HGF)0 |b 4 |
700 | 1 | _ | |a Vogt, Holger |0 P:(DE-HGF)0 |b 5 |
700 | 1 | _ | |a Federica, Villa |0 P:(DE-HGF)0 |b 6 |
700 | 1 | _ | |a Bronzi, Danilo |0 P:(DE-HGF)0 |b 7 |
700 | 1 | _ | |a Tisa, Simone |0 P:(DE-HGF)0 |b 8 |
700 | 1 | _ | |a Tosi, Alberto |0 P:(DE-HGF)0 |b 9 |
700 | 1 | _ | |a Zappa, Franco |0 P:(DE-HGF)0 |b 10 |
773 | _ | _ | |y 2014 |
856 | 4 | _ | |u https://juser.fz-juelich.de/record/153873/files/FZJ-2014-03352.pdf |y OpenAccess |
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