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@ARTICLE{Siemon:201482,
      author       = {Siemon, Anne and Menzel, Stephan and Waser, R. and Linn,
                      Eike},
      title        = {{A} {C}omplementary {R}esistive {S}witch-{B}ased {C}rossbar
                      {A}rray {A}dder},
      journal      = {IEEE journal on emerging and selected topics in circuits
                      and systems},
      volume       = {5},
      issn         = {2156-3357},
      address      = {New York, NY},
      publisher    = {IEEE},
      reportid     = {FZJ-2015-03777},
      pages        = {64 - 74},
      year         = {2015},
      abstract     = {Redox-based resistive switching devices (ReRAM) are an
                      emerging class of nonvolatile storage elements suited for
                      nanoscale memory applications. In terms of logic operations,
                      ReRAM devices were suggested to be used as programmable
                      interconnects, large-scale look-up tables or for sequential
                      logic operations. However, without additional selector
                      devices these approaches are not suited for use in large
                      scale nanocrossbar memory arrays, which is the preferred
                      architecture for ReRAM devices due to the minimum area
                      consumption. To overcome this issue for the sequential logic
                      approach, we recently introduced a novel concept, which is
                      suited for passive crossbar arrays using complementary
                      resistive switches (CRSs). CRS cells offer two high
                      resistive storage states, and thus, parasitic “sneak”
                      currents are efficiently avoided. However, until now the
                      CRS-based logic-in-memory approach was only shown to be able
                      to perform basic Boolean logic operations using a single CRS
                      cell. In this paper, we introduce two multi-bit adder
                      schemes using the CRS-based logic-in-memory approach. We
                      proof the concepts by means of SPICE simulations using a
                      dynamical memristive device model of a ReRAM cell. Finally,
                      we show the advantages of our novel adder concept in terms
                      of step count and number of devices in comparison to a
                      recently published adder approach, which applies the
                      conventional ReRAM-based sequential logic concept introduced
                      by Borghetti et al.},
      cin          = {PGI-7},
      ddc          = {620},
      cid          = {I:(DE-Juel1)PGI-7-20110106},
      pnm          = {521 - Controlling Electron Charge-Based Phenomena
                      (POF3-521)},
      pid          = {G:(DE-HGF)POF3-521},
      typ          = {PUB:(DE-HGF)16},
      UT           = {WOS:000351451000007},
      doi          = {10.1109/JETCAS.2015.2398217},
      url          = {https://juser.fz-juelich.de/record/201482},
}