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| Hauptseite > Publikationsdatenbank > Impact of Si cap, strain and temperature on the hole mobility of (s)Si/sSiGe/(s)SOI quantum-well p-MOSFETs > print |
| Hauptseite > Publikationsdatenbank > Impact of Si cap, strain and temperature on the hole mobility of (s)Si/sSiGe/(s)SOI quantum-well p-MOSFETs > print |
| 001 | 203147 | ||
| 005 | 20210129220307.0 | ||
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| 245 | _ | _ | |a Impact of Si cap, strain and temperature on the hole mobility of (s)Si/sSiGe/(s)SOI quantum-well p-MOSFETs |
| 260 | _ | _ | |a [S.l.] @ |c 2014 |b Elsevier |
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| 520 | _ | _ | |a Quantum-well p-MOSFETs are fabricated on (strained) Si/strained SiGe/(strained) SOI hetero-structure substrates and the effects of Si cap, strain and temperature on hole mobility are investigated. The Si cap layer which behaves as a passivation layer for the SiGe improves the hole mobility by suppressing the scattering due to charges in the high-κ layer and at the high-κ interface. High strain in SiGe enhances the Ge interdiffusion during the thermal process, leading to reduced hole mobilities. The transistors are also characterized at very low temperatures and the scattering mechanism is discussed. |
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| 700 | 1 | _ | |a Zhao, Y. |0 P:(DE-HGF)0 |b 3 |e Corresponding author |
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| 773 | _ | _ | |a 10.1016/j.mee.2013.06.015 |g Vol. 113, p. 5 - 9 |0 PERI:(DE-600)1497065-x |p 5 - 9 |t Microelectronic engineering |v 113 |y 2014 |x 0167-9317 |
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