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024 7 _ |2 DOI
|a 10.1007/s00339-011-6287-2
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|a WOS:000288253600003
024 7 _ |2 ISSN
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037 _ _ |a PreJuSER-21958
041 _ _ |a eng
082 _ _ |a 530
084 _ _ |2 WoS
|a Materials Science, Multidisciplinary
084 _ _ |2 WoS
|a Physics, Applied
100 1 _ |a Kügeler, C.
|b 0
|u FZJ
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245 _ _ |a Materials, technologies, and circuit concepts for nanocrossbar-based bipolar RRAM
260 _ _ |c 2011
|a Berlin
|b Springer
300 _ _ |a S1 791 - 809
336 7 _ |a Journal Article
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440 _ 0 |a Applied Physics A
|x 0947-8396
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|v 102
500 _ _ |3 POF3_Assignment on 2016-02-29
500 _ _ |a For their valuable contributions and fruitful discussions, the authors would like to thank C. Nauenheim, M. Meier, F. Lentz, S. Trellenkamp, J. Zhang, L. Yi, C. Schindler, R. Soni, L. Yang and S. Hoffmann-Eifert. The major part of this work was supported by the "Helmholtz Association of German Research Centres" within the framework of the additional funding project "Nanoarchitecture Lab".
520 _ _ |a The paper reports on the characterization of bipolar resistive switching materials and their integration into nanocrossbar structures, as well as on different memory operation schemes in terms of memory density and the challenging problem of sneak paths. TiO2, WO3, GeSe, SiO2 and MSQ thin films were integrated into nanojunctions of 100x100 nm(2). The variation between inert Pt and Cu or Ag top electrodes leads to valence change (VCM) switching or electrochemical metallization (ECM) switching and has significant impact on the resistive properties. All materials showed promising characteristics with switching speeds down to 10 ns, multilevel switching, good endurance and retention. Nanoimprint lithography was found to be a suitable tool for processing crossbar arrays down to a feature size of 50 nm and 3D stacking was demonstrated. The inherent occurrence of current sneak paths in passive crossbar arrays can be circumvented by the implementation of complementary resistive switching (CRS) cells. The comparison with other operation schemes shows that the CRS concept dramatically increases the addressable memory size to about 10(10) bit.
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700 1 _ |a Rosezin, R.
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700 1 _ |a Linn, E.
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700 1 _ |a Bruchhaus, R.
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700 1 _ |a Waser, R.
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773 _ _ |0 PERI:(DE-600)1398311-8
|a 10.1007/s00339-011-6287-2
|g Vol. 102, p. S1 791 - 809
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856 7 _ |u http://dx.doi.org/10.1007/s00339-011-6287-2
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