ExaNoDe

European Exascale Processor Memory Node Design

CoordinatorAtomic Energy and Alternative Energies Commission ; University of Manchester ; BARCELONA SUPERCOMPUTING CENTER - CENTRO NACIONAL DE SUPERCOMPUTACION ; Virtual Open Systems (France) ; KALRAY SA ; Forschungszentrum Jülich ; ARM LIMITED ; SCAPOS AG ; FRAUNHOFER GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V. ; IDRYMA TECHNOLOGIAS KAI EREVNAS ; BULL SAS ; Swiss Federal Institute of Technology in Zurich ; CNRS - Institut des Sciences Biologiques
Grant period2015-10-01 - 2019-06-30
Funding bodyEuropean Union
Call numberH2020-FETHPC-2014
Grant number671578
IdentifierG:(EU-Grant)671578

Note: ExaNoDe will investigate, develop integrate and validate the building blocks (technology readiness level 5) for a highly efficient, highly integrated, multi-way, high-performance, heterogeneous compute element aimed towards exascale computing. It will build on multiple European initiatives for scalable computing, utilizing low- power processors and advanced nanotechnologies. ExaNoDe will draw heavily on the Unimem memory and system design paradigm defined within the EUROSERVER FP7 project, providing low-latency, high-bandwidth and resilient memory access, scalable to Exabyte levels. The ExaNoDe compute element aims towards exascale compute goals through: • Integration of the most advanced low-power processors and accelerators (across scalar, SIMD, GPGPU and FPGA processing elements) supported by research and innovation in the deployment of associated nanotechnologies and in the mechanical requirements to enable the development of a high-density, high-performance integrated compute element with advanced thermal characteristics and connectivity to the next generation of system interconnect and storage; • Undertaking essential research to ensure the ExaNoDe compute element provides necessary support of HPC applications including I/O and storage virtualization techniques, operating system and semantically aware runtime capabilities and PGAS, OpenMP and MPI paradigms; • The development of a hardware emulation of interconnect to enable the evaluation of Unimem for the deployment of multiple compute elements and to leverage the potential of the ExaNoDe approach for HPC applications. Each aspect of ExaNoDe is aligned with the goals of the ETP4HPC. The work will be steered by first-hand experience and analysis of high-performance applications and their requirements; investigations being carried out with “mini-application” abstractions and the tuning of their kernels.
     

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http://join2-wiki.gsi.de/foswiki/pub/Main/Artwork/join2_logo100x88.png Contribution to a conference proceedings/Contribution to a book  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;
Mainstream vs. Emerging HPC: Metrics, Trade-Offs and Lessons Learned
2018 30th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD) : [Proceedings] - IEEE, 2018. - ISBN 978-1-5386-7769-8 - doi:10.1109/CAHPC.2018.8645891
2018 30th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), LyonLyon, France, 24 Sep 2018 - 27 Sep 20182018-09-242018-09-27
IEEE 250-257 () [10.1109/CAHPC.2018.8645891]  Download fulltext Files BibTeX | EndNote: XML, Text | RIS

http://join2-wiki.gsi.de/foswiki/pub/Main/Artwork/join2_logo100x88.png Journal Article
JSCs Horizon 2020
Innovatives Supercomputing in Deutschland 13(2), 64 () OpenAccess  Download fulltext Files  Download fulltextFulltext Download fulltextFulltext by OpenAccess repository BibTeX | EndNote: XML, Text | RIS

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 Datensatz erzeugt am 2015-09-13, letzte Änderung am 2023-02-13



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