%0 Conference Paper
%A Richter, Simon
%A Schulte-Braucks, Christian
%A Knoll, Lars
%A Luong, Gia Vinh
%A Schäfer, Anna
%A Trellenkamp, Stefan
%A Zhao, Qing-Tai
%A Mantl, Siegfried
%T Experimental demonstration of inverter and NAND operation in p-TFET logic at ultra-low supply voltages down to VDD = 0.15 V
%I IEEE
%M FZJ-2015-07818
%P 23-24
%D 2014
%X Tunnel-FETs (TFETs) have been studied extensively as a replacement for MOSFETs in the supply voltage regime below VDD = 0.3 V [1]. Due to the TFET ability for offering inverse subthreshold slopes SS below 60 mV/dec, these devices are promising candidates for power efficient integrated circuits. Extensive research has been carried out on the characteristics of single TFET devices [2][3] and first inverter structures have been realized as demonstration of simple logic circuits [4][5][6]. In this work, we present TFET logic circuits based on gate-all-around (GAA) Si nanowire (NW) array TFETs showing small SS and high Ion of 39 μA/μm at VDD = -1 V. This comparably high performance in Si TFETs was realized by a source formation via silicidation and dopant segregation. Using these devices inverters based on p-TFET logic and for the first time TFET NAND gates are demonstrated experimentally. The logic gates operate at ultra-low supply voltages down to VDD = 0.15 V.
%B 2014 72nd Annual Device Research Conference (DRC)
%C 22 Jun 2014 - 25 Jun 2014, Santa Barbara (CA)
Y2 22 Jun 2014 - 25 Jun 2014
M2 Santa Barbara, CA
%F PUB:(DE-HGF)8
%9 Contribution to a conference proceedings
%R 10.1109/DRC.2014.6872281
%U https://juser.fz-juelich.de/record/280071