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000280071 1001_ $$0P:(DE-Juel1)5960$$aRichter, Simon$$b0$$eCorresponding author
000280071 1112_ $$a2014 72nd Annual Device Research Conference (DRC)$$cSanta Barbara$$d2014-06-22 - 2014-06-25$$gDRC 2014$$wCA
000280071 245__ $$aExperimental demonstration of inverter and NAND operation in p-TFET logic at ultra-low supply voltages down to VDD = 0.15 V
000280071 260__ $$bIEEE$$c2014
000280071 300__ $$a23-24
000280071 3367_ $$0PUB:(DE-HGF)8$$2PUB:(DE-HGF)$$aContribution to a conference proceedings$$bcontrib$$mcontrib$$s1452684430_2870
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000280071 520__ $$aTunnel-FETs (TFETs) have been studied extensively as a replacement for MOSFETs in the supply voltage regime below VDD = 0.3 V [1]. Due to the TFET ability for offering inverse subthreshold slopes SS below 60 mV/dec, these devices are promising candidates for power efficient integrated circuits. Extensive research has been carried out on the characteristics of single TFET devices [2][3] and first inverter structures have been realized as demonstration of simple logic circuits [4][5][6]. In this work, we present TFET logic circuits based on gate-all-around (GAA) Si nanowire (NW) array TFETs showing small SS and high Ion of 39 μA/μm at VDD = -1 V. This comparably high performance in Si TFETs was realized by a source formation via silicidation and dopant segregation. Using these devices inverters based on p-TFET logic and for the first time TFET NAND gates are demonstrated experimentally. The logic gates operate at ultra-low supply voltages down to VDD = 0.15 V.
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000280071 7001_ $$0P:(DE-Juel1)161530$$aSchulte-Braucks, Christian$$b1
000280071 7001_ $$0P:(DE-HGF)0$$aKnoll, Lars$$b2
000280071 7001_ $$0P:(DE-Juel1)156277$$aLuong, Gia Vinh$$b3
000280071 7001_ $$0P:(DE-HGF)0$$aSchäfer, Anna$$b4
000280071 7001_ $$0P:(DE-Juel1)128856$$aTrellenkamp, Stefan$$b5
000280071 7001_ $$0P:(DE-Juel1)128649$$aZhao, Qing-Tai$$b6
000280071 7001_ $$0P:(DE-Juel1)128609$$aMantl, Siegfried$$b7
000280071 773__ $$a10.1109/DRC.2014.6872281
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