TY  - CONF
AU  - Richter, Simon
AU  - Schulte-Braucks, Christian
AU  - Knoll, Lars
AU  - Luong, Gia Vinh
AU  - Schäfer, Anna
AU  - Trellenkamp, Stefan
AU  - Zhao, Qing-Tai
AU  - Mantl, Siegfried
TI  - Experimental demonstration of inverter and NAND operation in p-TFET logic at ultra-low supply voltages down to VDD = 0.15 V
PB  - IEEE
M1  - FZJ-2015-07818
SP  - 23-24
PY  - 2014
AB  - Tunnel-FETs (TFETs) have been studied extensively as a replacement for MOSFETs in the supply voltage regime below VDD = 0.3 V [1]. Due to the TFET ability for offering inverse subthreshold slopes SS below 60 mV/dec, these devices are promising candidates for power efficient integrated circuits. Extensive research has been carried out on the characteristics of single TFET devices [2][3] and first inverter structures have been realized as demonstration of simple logic circuits [4][5][6]. In this work, we present TFET logic circuits based on gate-all-around (GAA) Si nanowire (NW) array TFETs showing small SS and high Ion of 39 μA/μm at VDD = -1 V. This comparably high performance in Si TFETs was realized by a source formation via silicidation and dopant segregation. Using these devices inverters based on p-TFET logic and for the first time TFET NAND gates are demonstrated experimentally. The logic gates operate at ultra-low supply voltages down to VDD = 0.15 V.
T2  - 2014 72nd Annual Device Research Conference (DRC)
CY  - 22 Jun 2014 - 25 Jun 2014, Santa Barbara (CA)
Y2  - 22 Jun 2014 - 25 Jun 2014
M2  - Santa Barbara, CA
LB  - PUB:(DE-HGF)8
DO  - DOI:10.1109/DRC.2014.6872281
UR  - https://juser.fz-juelich.de/record/280071
ER  -