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@ARTICLE{Zhao:280072,
author = {Zhao, Qing-Tai and Richter, Simon and Schulte-Braucks,
Christian and Knoll, Lars and Blaeser, Sebastian and Luong,
Gia Vinh and Trellenkamp, Stefan and Schäfer, Anna and
Tiedemann, Andreas and Hartmann, Jean-Michel and Bourdelle,
Konstantin and Mantl, Siegfried},
title = {{S}trained {S}i and {S}i{G}e {N}anowire {T}unnel {FET}s for
{L}ogic and {A}nalog {A}pplications},
journal = {IEEE journal of the Electron Devices Society},
volume = {3},
number = {3},
issn = {2168-6734},
address = {[New York, NY]},
publisher = {IEEE},
reportid = {FZJ-2015-07819},
pages = {103 - 114},
year = {2015},
abstract = {Guided by the Wentzel-Kramers-Brillouin approximation for
band-to-band tunneling (BTBT), various performance boosters
for Si TFETs are presented and experimentally verified.
Along this line, improvements achieved by the implementation
of uniaxial strain in nanowires (NW), the benefits of
high-k/metal gates, and newly engineered tunneling junctions
as well as the effect of scaling the NW to diameters of 10
nm are demonstrated. Specifically, self-aligned ion
implantation into the source/drain silicide and dopant
segregation has been exploited to achieve steep tunneling
junctions with less defects. The obtained devices deliver
high on-currents, e.g., gate-all-around (GAA) NW p-TFETs
with 10 nm diameter show ID = 64 μA/μm at VDS = VGS - Voff
= -1.0 V, and good inverse subthreshold slopes (SS).
Tri-gate TFETs reach minimum SS of 30 mV/dec. Dopant
segregation helps to minimize the defect density in the
junction and thus trap assisted tunneling (TAT) is reduced.
Pulsed current-voltage (I-V) measurements have been used to
investigate TAT. We could show that scaled NW devices with
multigates are less vulnerable to TAT compared to planar
devices due to a shorter tunneling path enabled by the
inherently good electrostatics. Furthermore, SiGe NW homo-
and heterojunction TFETs have been investigated. The
advantages of a SiGe/Si heterostructure as compared to a
homojunction device are revealed and the effect of line
tunneling which results in an increased BTBT generation is
demonstrated. It is also shown that complementary strained
Si TFET inverters and p-TFET NAND gates can be operated at
VDD as low as 0.2 V. This suggests a great potential of
TFETs for ultralow power applications. The analysis of GAA
NW TFETs for analog applications provided a high
transconductance efficiency and large intrinsic gain, even
higher than for state-of-the-art 20 nm FinFETs at low
voltages.},
cin = {PGI-9 / PGI-8-PT},
ddc = {620},
cid = {I:(DE-Juel1)PGI-9-20110106 / I:(DE-Juel1)PGI-8-PT-20110228},
pnm = {521 - Controlling Electron Charge-Based Phenomena
(POF3-521) / E2SWITCH - Energy Efficient Tunnel FET Switches
and Circuits (619509)},
pid = {G:(DE-HGF)POF3-521 / G:(EU-Grant)619509},
typ = {PUB:(DE-HGF)16},
UT = {WOS:000369884400005},
doi = {10.1109/JEDS.2015.2400371},
url = {https://juser.fz-juelich.de/record/280072},
}