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@ARTICLE{Goldrian:3225,
      author       = {Goldrian, G. and Huth, T. and Krill, B. and Lauritsen, J.
                      and Schick, H. and Ouda, I. and Heybrock, S. and Hierl, D.
                      and Maurer, T. and Meyer, N. and Schäfer, A. and Solbrig,
                      S. and Streuer, T. and Wettig, T. and Pleiter, D. and
                      Sulanke, K.-H. and Winter, F. and Simma, H. and Schifano,
                      S.F. and Tripiccione, R. and Nobile, A. and Drochner, M. and
                      Lippert, T. and Fodor, Z.},
      title        = {{QPACE}: {Q}uantum {C}hromodynamics {P}arallel {C}omputing
                      on the {C}ell {B}roadband {E}ngine},
      journal      = {Computing in science and engineering},
      volume       = {10},
      issn         = {1521-9615},
      address      = {College Park, Md.},
      publisher    = {Inst.},
      reportid     = {PreJuSER-3225},
      pages        = {46 - 54},
      year         = {2008},
      note         = {QPACE is funded by the Deutsche Forschungsgemeinschaft
                      (DFG) through the SFB/TR-55 framework and by IBM. We
                      gratefully acknowledge important contributions to QPACE by
                      Eurotech (Italy) and Knurr (Germany).},
      abstract     = {Application-driven computers for Lattice Gauge Theory
                      simulations have often been based on system-on-chip designs,
                      but the development costs can be prohibitive for academic
                      project budgets. An alternative approach uses compute nodes
                      based on a commercial processor tightly coupled to a
                      custom-designed network processor. Preliminary analysis
                      shows that this solution offers good performance, but it
                      also entails several challenges, including those arising
                      from the processor's multicore structure and from
                      implementing the network processor on a field-programmable
                      gate array.},
      keywords     = {J (WoSType)},
      cin          = {JSC / JARA-SIM},
      ddc          = {530},
      cid          = {I:(DE-Juel1)JSC-20090406 / I:(DE-Juel1)VDB1045},
      pnm          = {Scientific Computing},
      pid          = {G:(DE-Juel1)FUEK411},
      shelfmark    = {Computer Science, Interdisciplinary Applications},
      typ          = {PUB:(DE-HGF)16},
      UT           = {WOS:000260130800009},
      doi          = {10.1109/MCSE.2008.153},
      url          = {https://juser.fz-juelich.de/record/3225},
}