TY  - JOUR
AU  - Mustafa, J.
AU  - Waser, R.
TI  - Capacitive-resistive nondriven plateline cell architecture for RRAM technology
JO  - AEU - International Journal of Electronics and Communications
VL  - 60
SN  - 1434-8411
CY  - München
PB  - Elsevier
M1  - PreJuSER-58106
SP  - 459 - 461
PY  - 2006
N1  - Record converted from VDB: 12.11.2012
AB  - A new memory cell concept, which is appropriate for the use with resistive hysteretic memory elements is introduced. Resistive memories are one of the main memory development streams today. The introduced concept can be used to facilitate the integration with current CMOS technology, where no plateline is required. This is accomplished by using a capacitor, which is serially connected to the resistive element. (c) 2005 Elsevier GmbH. All rights reserved.
KW  - J (WoSType)
LB  - PUB:(DE-HGF)16
UR  - <Go to ISI:>//WOS:000238314000007
DO  - DOI:10.1016/j.aeue.2005.09.005
UR  - https://juser.fz-juelich.de/record/58106
ER  -