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@ARTICLE{Mustafa:58106,
      author       = {Mustafa, J. and Waser, R.},
      title        = {{C}apacitive-resistive nondriven plateline cell
                      architecture for {RRAM} technology},
      journal      = {AEU - International Journal of Electronics and
                      Communications},
      volume       = {60},
      issn         = {1434-8411},
      address      = {München},
      publisher    = {Elsevier},
      reportid     = {PreJuSER-58106},
      pages        = {459 - 461},
      year         = {2006},
      note         = {Record converted from VDB: 12.11.2012},
      abstract     = {A new memory cell concept, which is appropriate for the use
                      with resistive hysteretic memory elements is introduced.
                      Resistive memories are one of the main memory development
                      streams today. The introduced concept can be used to
                      facilitate the integration with current CMOS technology,
                      where no plateline is required. This is accomplished by
                      using a capacitor, which is serially connected to the
                      resistive element. (c) 2005 Elsevier GmbH. All rights
                      reserved.},
      keywords     = {J (WoSType)},
      cin          = {IFF-IEM / IFF-6 / CNI / JARA-FIT},
      ddc          = {004},
      cid          = {I:(DE-Juel1)VDB321 / I:(DE-Juel1)VDB786 /
                      I:(DE-Juel1)VDB381 / $I:(DE-82)080009_20140620$},
      pnm          = {Grundlagen für zukünftige Informationstechnologien},
      pid          = {G:(DE-Juel1)FUEK412},
      shelfmark    = {Engineering, Electrical $\&$ Electronic /
                      Telecommunications},
      typ          = {PUB:(DE-HGF)16},
      UT           = {WOS:000238314000007},
      doi          = {10.1016/j.aeue.2005.09.005},
      url          = {https://juser.fz-juelich.de/record/58106},
}