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001     58106
005     20190625112120.0
024 7 _ |2 DOI
|a 10.1016/j.aeue.2005.09.005
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041 _ _ |a eng
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|a Engineering, Electrical & Electronic
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100 1 _ |0 P:(DE-HGF)0
|a Mustafa, J.
|b 0
245 _ _ |a Capacitive-resistive nondriven plateline cell architecture for RRAM technology
260 _ _ |a München
|b Elsevier
|c 2006
300 _ _ |a 459 - 461
336 7 _ |a Journal Article
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440 _ 0 |0 17021
|a AEÜ : International Journal of Electronics and Communications
|v 60
|x 1434-8411
500 _ _ |a Record converted from VDB: 12.11.2012
520 _ _ |a A new memory cell concept, which is appropriate for the use with resistive hysteretic memory elements is introduced. Resistive memories are one of the main memory development streams today. The introduced concept can be used to facilitate the integration with current CMOS technology, where no plateline is required. This is accomplished by using a capacitor, which is serially connected to the resistive element. (c) 2005 Elsevier GmbH. All rights reserved.
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653 2 0 |2 Author
|a resistive hysteretic elements
653 2 0 |2 Author
|a nondriven plateline
653 2 0 |2 Author
|a nonvolatile
653 2 0 |2 Author
|a RRAM
700 1 _ |0 P:(DE-Juel1)131022
|a Waser, R.
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