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000808932 0247_ $$2Handle$$a2128/10433
000808932 0247_ $$2URN$$aurn:nbn:de:0001-2016063011
000808932 0247_ $$2ISSN$$a1866-1807
000808932 020__ $$a978-3-95806-135-4
000808932 037__ $$aFZJ-2016-02452
000808932 041__ $$aEnglish
000808932 1001_ $$0P:(DE-Juel1)145410$$aBlaeser, Sebastian$$b0$$eCorresponding author$$gmale$$ufzj
000808932 245__ $$aStrained Silicon-Germanium/Silicon Heterostructure Tunnel FETs for Low Power Applications$$f- 2016-04-29
000808932 260__ $$aJülich$$bForschungszentrum Jülich GmbH Zentralbibliothek, Verlag$$c2016
000808932 300__ $$aIV, 91, XVII S.
000808932 3367_ $$2DataCite$$aOutput Types/Dissertation
000808932 3367_ $$2ORCID$$aDISSERTATION
000808932 3367_ $$2BibTeX$$aPHDTHESIS
000808932 3367_ $$02$$2EndNote$$aThesis
000808932 3367_ $$0PUB:(DE-HGF)11$$2PUB:(DE-HGF)$$aDissertation / PhD Thesis$$bphd$$mphd$$s1467266790_21172
000808932 3367_ $$2DRIVER$$adoctoralThesis
000808932 4900_ $$aSchriften des Forschungszentrums Jülich. Reihe Schlüsseltechnologien / Key Technologies$$v124
000808932 502__ $$aRWTH Aachen, Diss., 2016$$bDr.$$cRWTH Aachen$$d2016
000808932 520__ $$aScaling of nanoelectronics consequently comes along with power consumption in integrated circuits, either in terms of static power consumption P$_{static}$ due to different leakage contributions or in terms of dynamic power consumption P$_{dynamic}$, accounting for the power density arising in an integrated circuit and thus, restricting an arbitrary miniaturization. Since dynamic power consumption scales with the second power of the supply voltage, P$_{dynamic} \varpropto V^{2}_{DD}$, a reduction of the latter represents a promising approach in order to enable low power electronics. However, a reduction of the supply voltage V$_{DD}$ inevitably results in an either lowered on-current I$_{on}$ or increased off-current I$_{off}$ of a metal-oxide-semiconductor field-effect transistor (MOSFET). A reduction of the subthreshold swing $\textit{SS}$ of the transistor as a measure of the steepness of its transition from the off- to the on-state in turn allows for a reduction of the supply voltage V$_{DD}$ without accepting an either lowered on-current I$_{on}$ or increased off-current I$_{off}$. However, since charge transport in a MOSFET is based on thermionic emission over a potential barrier due to a broadened Fermi distribution function, its subthreshold swing $\textit{SS}$ is limited to 60mV/dec at room temperature T = 300K. In order to overcome this inherent limitation of a MOSFET and allow for a smaller subthreshold swing $\textit{SS}$, the tunnel field-effect transistor (TFET) has been suggested as a promising alternative due to its charge transport realized by means of quantum mechanical band-to-band tunneling (BTBT). Within the framework of this thesis, two different proposals of a TFET device concept allowing for low power applications are investigated. As a first approach, a vertical Silicon-Germanium/Silicon (SiGe/Si) heterostructure TFET is considered which makes use ofstrained SiGe as a material with smaller band gap E$_{g}$ at the source tunnel junction in order to increase the probability for BTBT while suppressing the ambipolar switching characteristics in parallel due to the use of Si with its higher band gap E$_{g}$ as compared to SiGe at the drain tunnel junction, thus enabling a heterostructure device concept. As a second approach, a planar SiGe/Si heterostructure TFET is presented which not only makes use of strained SiGe as a material with smaller band gap E$_{g}$ at the source tunnel junction, but also benefits from a selective and self-adjusted silicidation in combination with a counter doped pocket at the source tunnel junction in order to enable line tunneling aligned with the gate electric field lines in an enlarged area directly underneath the gate. In addition, for both types of TFETs, technology computer aided design (TCAD) simulations are consulted in order to evaluate the respective experimental results as well as to illustrate potential improvements of each device concept. [...]
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