% IMPORTANT: The following is UTF-8 encoded.  This means that in the presence
% of non-ASCII characters, it will not work with BibTeX 0.99 or older.
% Instead, you should use an up-to-date BibTeX implementation like “bibtex8” or
% “biber”.

@ARTICLE{Luong:821161,
      author       = {Luong, Gia Vinh and Strangio, S. and Tiedemann, Andreas and
                      Lenk, S. and Trellenkamp, S. and Bourdelle, K. K. and Zhao,
                      Qing-Tai and Mantl, S.},
      title        = {{E}xperimental demonstration of strained {S}i nanowire
                      {GAA} n-{TFET}s and inverter operation with complementary
                      {TFET} logic at low supply voltages},
      journal      = {Solid state electronics},
      volume       = {115},
      number       = {Part B},
      issn         = {0038-1101},
      address      = {Oxford [u.a.]},
      publisher    = {Pergamon, Elsevier Science},
      reportid     = {FZJ-2016-06399},
      pages        = {152 - 159},
      year         = {2016},
      abstract     = {n this work, strained Si (sSi) nanowire array of n-TFETs
                      with gates all around (GAA) yielding ON-currents of 5
                      μA/μm at a supply voltage Vdd = 0.5 V are presented.
                      Tilted ion implantation with BF2+ into NiSi2 dopant has been
                      used to form a highly doped pocket for the source to channel
                      tunneling junction. These devices indicate sub-threshold
                      slopes (SS) below 60 mV/dec for Id < 10−4 μA/μm at Vds =
                      0.1 V at room temperature. Common analog device
                      characteristics have been determined at Vdd = 0.5 V
                      resulting in a transconductance gm = 24 μS/μm,
                      transconductance efficiency gm/Id = 23 V−1 and the
                      conductance gd = 0.8 μS/μm normalized to the gate width.
                      Based on the good saturation behavior in the output
                      characteristic, an intrinsic gain of 188 is observed. In
                      addition, we present operation of the first experimental sSi
                      GAA NW C-TFET inverter. In spite of ambipolar behavior, the
                      voltage transfer curves (VTC) indicate wide and constant
                      noise margin levels with steep transitions offering a
                      voltage gain of 25 at Vdd = 1 V.},
      cin          = {PGI-9 / JARA-FIT / PGI-8-PT},
      ddc          = {530},
      cid          = {I:(DE-Juel1)PGI-9-20110106 / $I:(DE-82)080009_20140620$ /
                      I:(DE-Juel1)PGI-8-PT-20110228},
      pnm          = {521 - Controlling Electron Charge-Based Phenomena
                      (POF3-521)},
      pid          = {G:(DE-HGF)POF3-521},
      typ          = {PUB:(DE-HGF)16},
      UT           = {WOS:000365614500013},
      doi          = {10.1016/j.sse.2015.08.020},
      url          = {https://juser.fz-juelich.de/record/821161},
}